Vamiga: Test CPU/C/CLR2.l fails

[dirkwhoffmann]

A500 8A: 🥰

vAmiga: 🙉

In the first line, this test runs instructionCLR.L ($10,a5) with a5 = COLOR00 - $10. The red arrow marks the point where the CLR instruction reads COLOR00, and the yellow arrow marks the point where CLR writes $0.

I think this test reveals that the CLR.L instruction writes the target operand in reversed order, i.e., $DFF182 is cleared before $DFF180. The total cycle counts are all OK (which was expected, because I already checked the instruction with cputester).

[dirkwhoffmann]

Fixed.

Old code:

template<Instr I, Mode M, Size S> void
Moira::execClr(u16 opcode)
{
    int dst = _____________xxx(opcode);

    u32 ea, data;
    if (!readOp<M,S, STD_AE_FRAME>(dst, ea, data)) return;

    isMemMode(M) ? prefetch() : prefetch<POLLIPL>();

    if (S == Long && isRegMode(M)) sync(2);
    writeOp <M,S, POLLIPL> (dst, ea, 0);

    reg.sr.n = 0;
    reg.sr.z = 1;
    reg.sr.v = 0;
    reg.sr.c = 0;
}

To fix the issue, line

    writeOp <M,S, POLLIPL> (dst, ea, 0);

had to be replaced by:

    writeOp <M,S, REVERSE | POLLIPL> (dst, ea, 0);

[mithrendal]

What about ORI.L

Does he maybe need ReverseOrder treatment too?

[dirkwhoffmann]

This is the timing signature of ANDI, his twin brother:

As you can clearly see: Yes

vAmiga already reverses the order:

template<Instr I, Mode M, Size S> void
Moira::execAndiEa(u16 opcode)
{
    u32 ea, data, result;

    u32 src = readI<S>();
    int dst = _____________xxx(opcode);

    if (!readOp<M,S, STD_AE_FRAME>(dst, ea, data)) return;

    result = logic<I,S>(src, data);
    prefetch();

    writeOp <M,S, POLLIPL | REVERSE> (dst, ea, result);
}