Vamiga: Test jump1b fails

[dirkwhoffmann]

With this test I was not only able to outsmart vAmiga, but also UAE:

A500 8A: 🥰

UAE: 🤭

[dirkwhoffmann]

It would be interesting to see how this test performs on the old Agnus.

Unfortunately, I haven't been successful in modifying the Alpine9000 tool chain such that it produces valid exe files 😕.

[dirkwhoffmann]

A closer look shows that the second COP2JMP write is emulated with the standard two-cycle delay in UAE. On the real machine, there is a one-cycle delay, only. The quick-jump condition (which allows a quick-jump only in cycle 0xE1) might be wrong in UAE.

[mithrendal]

Will check old agnus this weekend. 🤤👍🏻

[mithrendal]

A1000

[tonioni]

COPJMP sequence was the wrong way around. First cycle does not need free cycle and second does. I thought I already checked this carefully enough years ago when I got logic analyzer but I guess I didn't check all possible conditions.

Here few moments ago done quick logic analyzer cycle diagram results:

....8A ...BPL ...BPL ...BPL 1FE[1] ...BPL ....8C
....8A ...BPL .8C[1] ...BPL 1FE[2] ...BPL ...BPL ...BPL ....8C
....8A ...BPL .8C[1] ...BPL ...BPL ...BPL 1FE[2] ...BPL ....8C
....8A ...BPL ...BPL ...BPL 1FE[1] ...BPL ...BPL ...BPL ....8C
....8A ------ .8C[1] ...BPL ...BPL ...BPL 1FE[2] ...BPL ...BPL ...BPL ....8C
....8A ------ .8C[1] ------ 1FE[2] ...... ....8C

8A = write to COPJMP2, starts COPJMP sequence.
BPL = bitplane DMA cycle that is not available for copper. (I used different bitplane counts to simulate different free cycles)
8C[] = first COPJMP cycle. This gets skipped if cycle is not free but used by copper (so cpu/blitter can't use it) if it was free for the copper. Write to 8C from old pointer, pointer increased by 2 if cycle was done.
1FE[] = second COPJMP cycle (dummy write to 1FE). Requires free cycle.
8C = first fetch from new copper pointer
----- = free cycle

[1] = if cycle read old pointer (first instruction after COPJMP)
[2] = if cycle read old pointer + 2 (second instruction after COPJMP)

[dirkwhoffmann]

done quick logic analyzer cycle diagram

Wow, that was quick. Thanks a lot for investigation this and for the detailed description above!