Corefreq: CCD/CCX topology, cpuidle and cpufreq governor not working on AMD 3970X
The insmod should be enough if acpi_cpufreq is unloaded or am I missing something?
insmod corefreqk.ko Register_CPU_Freq=1 Register_CPU_Idle=1 Experimental=1 Register_Governor=1
dmesg:
[13864.517170] calling CoreFreqK_init+0x0/0x1000 [corefreqk] @ 927568
[13864.780352] CoreFreq(0:32): Processor [ 8F_31] Architecture [Zen2/Castle Peak] SMT [64/64]
[13864.780950] initcall CoreFreqK_init+0x0/0x1000 [corefreqk] returned 0 after 257588 usecs
cmdline relavant part: idle=halt
kernel config:
https://pastebin.com/ja0d9518
justanerd
All 108 comments
Hello,
Register_CPU_Idleis not implemented for AMD butRegister_CPU_Freq&Register_Governorare.Do you confirm from
/proc/modulesthat any previous registeredcpufreqis unloaded ?
The current has to be force removed (_b/c Kernel does not like to live without a cpufreq driver once registered ! some Mutex reasons according to its source code_)My SysLinux/ArchLinux command line, for an Intel Westmere W3690` is the folowing:
BOOT_IMAGE=../vmlinuz-linux root=/dev/disk/by-label/ROOT rw rootdelay=0 quiet loglevel=3 rd.udev.log-priority=3 break=n agp=off ipv6.disable=1 selinux=0 plymouth.enable=0 consoleblank=0 vt.color=0x03 nmi_watchdog=0 modprobe.blacklist=pcspkr,iTCO_wdt,acpi_cpufreq,pcc_cpufreq,intel_cstate,intel_uncore,intel_powerclamp,i7core_edac,i5500_temp,coretemp,asus_atk0110,nouveau idle=halt intel_pstate=disable cpufreq.off=0 pcie_aspm=off intremap=off cpu0_hotplug audit=0 intel_idle.max_cstate=0 sysrq_always_enabled=1 acpi_enforce_resources=lax iommu=pt initrd=../intel-ucode.img,../initramfs-linux.img
- Btw: if you boot with Kernel parameter
cpufreq.off=1, then _CoreFreq_ should take the leadership on the P-States (no driver options required).
cyring
on 24 Apr 2020
I tried cpufreq.off=1 corefreq-cli shows all drivers off
Any way to verify if the P-State control is working?
justanerd
on 24 Apr 2020
I tried cpufreq.off=1 corefreq-cli shows all drivers off
Any way to verify if the P-State control is working?
Yes, if you can increase the Max or any Boosted 1C , 2C ; it means that my driver is in control of the P-States. The Target TGT is also related to P-States, as a limiter.
_Please, gently raise the frequently ratio with one bin, as a starter_
cyring
on 24 Apr 2020
I tried to change all the PSTATE settings I can choose the ratios but they will not get applied.
justanerd
on 15 May 2020
Was this on the master branch ? May-be try the current develop
cyring
on 15 May 2020
I forgot to say : Core Performance Boost has to be disabled prior setting new ratios
I saw BIOS screenshots calling it Manual OC
- Go to the
Technologieswindow and press Turbo OFF
cyring
on 15 May 2020
That worked. Sadly I can't increase past 3.7Ghz.
justanerd
on 16 May 2020
That worked. Sadly I can't increase past 3.7Ghz.
Did you get a stable frequency ?
For the whole Processor or for distinct Core(s) ?
What's the max frequency ratio you can set in BIOS or other tools ?
cyring
on 16 May 2020
That worked. Sadly I can't increase past 3.7Ghz.
Did you get a stable frequency ?
Yes
For the whole Processor or for distinct Core(s) ?
whole
What's the max frequency ratio you can set in BIOS or other tools ?
With https://github.com/r4m0n/ZenStates-Linux I can enable the OC mode for all core to whatever I want. But the P-State stuff is also not working with higher frequencies.
justanerd
on 16 May 2020
3970X is advertized with a frequency boost up to 4.5 GHz. How high your BIOS let you set in manual OC ?
Do you them read the same frequency ratio between BIOS and CoreFreq and Kernel ?
cyring
on 16 May 2020
I haven't tried the Custom P-State option yet but with a static divider I
can set what ever I want.
I mostly run the system with PBO because all core overclocks are not good
for single core performance.
On Sat, May 16, 2020 at 6:52 PM CYRIL INGENIERIE notifications@github.com
wrote:
3970X is advertized with a frequency boost up to 4.5 GHz. How high your
BIOS let you set in manual OC ?
Do you them read the same frequency ratio between BIOS and Kernel ?—
You are receiving this because you authored the thread.
Reply to this email directly, view it on GitHub
https://github.com/cyring/CoreFreq/issues/181#issuecomment-629675000,
or unsubscribe
https://github.com/notifications/unsubscribe-auth/AAF7RJKB2GRG75G6DK7PT33RR3AFZANCNFSM4MP656SQ
.
justanerd
on 16 May 2020
Hello,
Could you try the develop branch and post back the Topology in text mode:
corefreq-cli -s -m
Thank you
cyring
on 26 May 2020
sure
output.txt
justanerd
on 26 May 2020
I'm not sure about the caches size: with 64 x SMT Cores, I'm decoding for a double value, compared to AMD datasheet.
Can you tell which sum is written for L1 L2 L3 in the UI header ?
cyring
on 26 May 2020
justanerd
on 26 May 2020
Thanks.
AMD says:
Total cache L1 = 2MB
Total cache L2 = 16MB
Total cache L3 = 128MB
Considering 32 physical Cores, L1 and L2 unit size in KB is ok, but L3 is wrong.
Still searching but I'm using the same algorithm for Ryzen and Threadripper
cyring
on 26 May 2020
Hello,
I'm rolling back to the AMD L3 cache size formula where register is given in 512 KB units.
Can you pull and try the latest develop branch.
Thank you.
cyring
on 26 May 2020
Hello,
I'm trying to read the thermal sensor per node which to my understanding counts more than one with EPYC & Threadripper
Could you please try the develop version. Once UI is running go to Settings > Thermal scope and change it to Thread, such as below.
cyring
on 21 Jun 2020
justanerd
on 21 Jun 2020
Thanks for trying
Regards
cyring
on 21 Jun 2020
Hello,
Among the last changes in issue #195 , an I/O ASM access to the FCH have been added: can you please check if the last _CoreFreq_ version is starting fine ?
Thank you
cyring
on 6 Jul 2020
Yes, runs fine.
justanerd
on 7 Jul 2020
Yes, runs fine.
Thank you very much
cyring
on 7 Jul 2020
Hello,
For your testings, the cpufreq is available in the develop branch
You will have to blacklist any current cpufreq driver, like acpi-cpufreq, to leave the room to the _CoreFreq_ driver
CoreFreq's cpufreq can be registered from its kernel module using these two options:
insmod corefreqk.ko Register_CPU_Freq=1 Register_Governor=1
_or_ from the Client: you first register the governor then CPU-Freq
Remark: CPU-Idle is not implemented yet.
Once CoreFreq's cpufreq well registered, you can play with:
freq=3500000; for cpu in /sys/devices/system/cpu/cpufreq/policy*/scaling_setspeed ; do echo $freq > $cpu; done
### where freq is one of your available frequencies (ratio shown in cyan color)
echo 0 > /sys/devices/system/cpu/cpufreq/boost
echo 1 > /sys/devices/system/cpu/cpufreq/boost
### and many other file attributes in the tree /sys/devices/system/cpu/cpufreq
Any change made on command line should be reflected in the UI
Cyril
cyring
on 18 Aug 2020
Hello,
In the develop branch is available a fix to monitor the temperature per CCD.
Could you please try with the Threadripper ?
- You go into
Settingsand change theThermal scopetoCoreorThread; next you stress per CPU with theTools > Turbo Select CPU...
If things works OK, CPUs belonging to the same CCD should raise their temperature together.
cyring
on 3 Sep 2020
It shows temps but they are completely in sync.
justanerd
on 4 Sep 2020
It shows temps but they are completely in sync.
Thanks for testing.
Can you post the full output of the topology using corefreq-cli -m
I have to check the CCD resulting of Threadripper
Be aware you have to stress differently CPUs to observe temps
You can now switch to the master branch
cyring
on 4 Sep 2020
justanerd
on 4 Sep 2020
- Very valuable output which shows that my CCD topology has an issue with more than 2 dies
https://github.com/cyring/CoreFreq/blob/d9e0202ccc792ff0047597401df7451b3a7baa44/corefreqk.c#L1718 - Referring to the EPYC PPR specifications, the architecture can go up to 8 CCDs with single and dual sockets
cyring
on 4 Sep 2020
Hello,
In the
developbranch is available a fix to enumerate the CCD and CCX identifiers.
Can you please provide the topology output ?To my understanding CCX refers to the L3 cache shared by a group of 4 cores; whereas CCD is the complex die gathering 8 Cores
Fyi here is my Ryzen 3950X map:
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 65536 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 65536 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 65536 16w
003: 0 6 0 0 3 0 32 8 32 8 512 8 i 65536 16w
004: 0 8 0 1 4 0 32 8 32 8 512 8 i 65536 16w
005: 0 10 0 1 5 0 32 8 32 8 512 8 i 65536 16w
006: 0 12 0 1 6 0 32 8 32 8 512 8 i 65536 16w
007: 0 14 0 1 7 0 32 8 32 8 512 8 i 65536 16w
008: 0 16 1 0 8 0 32 8 32 8 512 8 i 65536 16w
009: 0 18 1 0 9 0 32 8 32 8 512 8 i 65536 16w
010: 0 20 1 0 10 0 32 8 32 8 512 8 i 65536 16w
011: 0 22 1 0 11 0 32 8 32 8 512 8 i 65536 16w
012: 0 24 1 1 12 0 32 8 32 8 512 8 i 65536 16w
013: 0 26 1 1 13 0 32 8 32 8 512 8 i 65536 16w
014: 0 28 1 1 14 0 32 8 32 8 512 8 i 65536 16w
015: 0 30 1 1 15 0 32 8 32 8 512 8 i 65536 16w
016: 0 1 0 0 0 1 32 8 32 8 512 8 i 65536 16w
017: 0 3 0 0 1 1 32 8 32 8 512 8 i 65536 16w
018: 0 5 0 0 2 1 32 8 32 8 512 8 i 65536 16w
019: 0 7 0 0 3 1 32 8 32 8 512 8 i 65536 16w
020: 0 9 0 1 4 1 32 8 32 8 512 8 i 65536 16w
021: 0 11 0 1 5 1 32 8 32 8 512 8 i 65536 16w
022: 0 13 0 1 6 1 32 8 32 8 512 8 i 65536 16w
023: 0 15 0 1 7 1 32 8 32 8 512 8 i 65536 16w
024: 0 17 1 0 8 1 32 8 32 8 512 8 i 65536 16w
025: 0 19 1 0 9 1 32 8 32 8 512 8 i 65536 16w
026: 0 21 1 0 10 1 32 8 32 8 512 8 i 65536 16w
027: 0 23 1 0 11 1 32 8 32 8 512 8 i 65536 16w
028: 0 25 1 1 12 1 32 8 32 8 512 8 i 65536 16w
029: 0 27 1 1 13 1 32 8 32 8 512 8 i 65536 16w
030: 0 29 1 1 14 1 32 8 32 8 512 8 i 65536 16w
031: 0 31 1 1 15 1 32 8 32 8 512 8 i 65536 16w
- If you find the Threadripper map OK, can you also try the per CCD temperature ?
Thank you
cyring
on 4 Sep 2020
looks better:
justanerd
on 4 Sep 2020
zenpower output for reference:
justanerd
on 4 Sep 2020
Thanks for your return.
Do you mind to post the topology output ?
To my concern, I don't understand why some groups of temperature remain at zero:
- wrong address or no SMU register is backing the group ?
- is the Threadripper CCD numbering different from Epyc and/or Ryzen ?
a bug in the _CoreFreq_ collect ?
Here showing my Ryzen case:
We can see a CCD at 36° , the other one at 51°C
cyring
on 4 Sep 2020
justanerd
on 4 Sep 2020
Warning: if you are using another monitoring tool while _CoreFreq_ is running, then my driver has to be built in a special way to share a kernel mutex among all tools going through the SMU (presuming they are doing the same)
The build for a _kernel protected SMU access_ is:
make HWM_CHIPSET=COMPATIBLE clean all
Remark HWM_CHIPSET=COMPATIBLE has not been intensively tested. So If you rather want to stay with the _CoreFreq_ driver standard way:
make clean all
then you have to make to sure no other software and their respective driver are not accessing the SMU: zenpower being one of them.
cyring
on 4 Sep 2020
New change again in the develop branch to count 4 Cores per CCD
_Previous results don't look like any screenshots of Threadrippers I can see on the Internet_
Sorry for this new change and thank you for providing the topology output.
cyring
on 4 Sep 2020
First and third temps are always the same.
topology:
https://pastebin.ubuntu.com/p/S3sCNfghK9/
justanerd
on 7 Sep 2020
First and third temps are always the same.
Thank you for your returns
Based on the PPR specs above, it appears that one every two CCD is wired; may be because of the Threadripper design.
Based on the current develop branch, could you replace this source code:
https://github.com/cyring/CoreFreq/blob/dba5cc60d7f1fda33ef027e65d3072b6e6aa1698/corefreqk.c#L11023
with this:
Core_AMD_SMN_Read( TccdSensor,
SMU_AMD_THM_TCTL_CCD_REGISTER_F17H
+ ((2 * Core->T.Cluster.CCD) << 2),
SMU_AMD_INDEX_REGISTER_F17H,
SMU_AMD_DATA_REGISTER_F17H );
Please build, reload driver all and test temperatures.
Fyi, this change is interlacing the CCD when querying the SMU for sensors; a series of computed IDs, as follows 0 2 4 6
cyring
on 7 Sep 2020
looks better now:
justanerd
on 7 Sep 2020
first and last CCX still have the same temperature
justanerd
on 7 Sep 2020
first and last CCX still have the same temperature
Probably applying load per CPU may help to understand the temperature relatively to the CCD and CCX clusters.
Sharing my readings of the specs:
up to eight core/cache complex dies (CCD) and a single I/O die (IOD).
SP3 consists of from two to eight CCDs plus one IOD
The two CCXs of a CCD share a single GMI2 Fabric port to the IOD.
A single CCX consists of ... Four cores ... single-thread mode (1T) or two-thread SMT mode (2T)
I'm trying to find in specs for a discriminant register to refine the topology among the 8 x CCD registers.
We could also _count_ the CCD ID based on the architecture code-name but we have to consider the 3990X case and other EPYC 64 Cores where all the 8 CCD should be wired; and where the above code trick won't make it.
cyring
on 7 Sep 2020
Can you please post the CPUID dump
corefreq-cli -u
I'm especially interested by the latest physical Core of your Threadripper which would be CPU #31
cyring
on 7 Sep 2020
justanerd
on 7 Sep 2020
Can you please output this ?
lspci -n
00:00.0 0600: 1022:1480
00:00.2 0806: 1022:1481
00:01.0 0600: 1022:1482
00:02.0 0600: 1022:1482
00:03.0 0600: 1022:1482
00:04.0 0600: 1022:1482
00:05.0 0600: 1022:1482
00:07.0 0600: 1022:1482
00:07.1 0604: 1022:1484
00:08.0 0600: 1022:1482
00:08.1 0604: 1022:1484
00:14.0 0c05: 1022:790b (rev 61)
00:14.3 0601: 1022:790e (rev 51)
00:18.0 0600: 1022:1490
00:18.1 0600: 1022:1491
00:18.2 0600: 1022:1492
00:18.3 0600: 1022:1493
00:18.4 0600: 1022:1494
00:18.5 0600: 1022:1495
00:18.6 0600: 1022:1496
00:18.7 0600: 1022:1497
01:00.0 1300: 1022:148a
02:00.0 1300: 1022:1485
02:00.3 0c03: 1022:148c
20:00.0 0600: 1022:1480
20:00.2 0806: 1022:1481
20:01.0 0600: 1022:1482
20:02.0 0600: 1022:1482
20:03.0 0600: 1022:1482
20:03.1 0604: 1022:1483
20:04.0 0600: 1022:1482
20:05.0 0600: 1022:1482
20:07.0 0600: 1022:1482
20:07.1 0604: 1022:1484
20:08.0 0600: 1022:1482
20:08.1 0604: 1022:1484
21:00.0 0300: 10de:1b06 (rev a1)
21:00.1 0403: 10de:10ef (rev a1)
22:00.0 1300: 1022:148a
23:00.0 1300: 1022:1485
23:00.1 1080: 1022:1486
23:00.3 0c03: 1022:148c
40:00.0 0600: 1022:1480
40:00.2 0806: 1022:1481
40:01.0 0600: 1022:1482
40:01.1 0604: 1022:1483
40:02.0 0600: 1022:1482
40:03.0 0600: 1022:1482
40:03.1 0604: 1022:1483
40:03.2 0604: 1022:1483
40:03.3 0604: 1022:1483
40:03.4 0604: 1022:1483
40:04.0 0600: 1022:1482
40:05.0 0600: 1022:1482
40:07.0 0600: 1022:1482
40:07.1 0604: 1022:1484
40:08.0 0600: 1022:1482
40:08.1 0604: 1022:1484
41:00.0 0604: 1022:57ad
42:01.0 0604: 1022:57a3
42:02.0 0604: 1022:57a3
42:03.0 0604: 1022:57a3
42:04.0 0604: 1022:57a3
42:05.0 0604: 1022:57a3
42:08.0 0604: 1022:57a4
42:09.0 0604: 1022:57a4
42:0a.0 0604: 1022:57a4
43:00.0 0108: 144d:a808
44:00.0 0200: 8086:1563 (rev 01)
44:00.1 0200: 8086:1563 (rev 01)
46:00.0 0c03: 1b21:2142
47:00.0 0106: 1b21:0612 (rev 02)
48:00.0 0280: 8086:2723 (rev 1a)
49:00.0 1300: 1022:1485
49:00.1 0c03: 1022:149c
49:00.3 0c03: 1022:149c
4a:00.0 0106: 1022:7901 (rev 51)
4b:00.0 0106: 1022:7901 (rev 51)
4c:00.0 0108: 144d:a808
4d:00.0 0108: 1987:5012 (rev 01)
4e:00.0 0108: 144d:a808
4f:00.0 0108: 144d:a808
50:00.0 1300: 1022:148a
51:00.0 1300: 1022:1485
60:00.0 0600: 1022:1480
60:00.2 0806: 1022:1481
60:01.0 0600: 1022:1482
60:02.0 0600: 1022:1482
60:03.0 0600: 1022:1482
60:04.0 0600: 1022:1482
60:05.0 0600: 1022:1482
60:07.0 0600: 1022:1482
60:07.1 0604: 1022:1484
60:08.0 0600: 1022:1482
60:08.1 0604: 1022:1484
61:00.0 1300: 1022:148a
62:00.0 1300: 1022:1485
justanerd
on 7 Sep 2020
Thanks.
I was expecting to decode this statement from the Specs:
The processor includes configuration space registers located in both BCS and ECS. Processor configuration space is accessed through bus 0, devices 18h to 1Fh, where device 18h corresponds to node 0 and device 1Fh corresponds to node 7
and find one device per enabled CCD; but in fact, comparing to my 3950X ...
00:00.0 0600: 1022:1480
00:00.2 0806: 1022:1481
00:01.0 0600: 1022:1482
00:01.1 0604: 1022:1483
00:01.2 0604: 1022:1483
00:02.0 0600: 1022:1482
00:03.0 0600: 1022:1482
00:03.1 0604: 1022:1483
00:04.0 0600: 1022:1482
00:05.0 0600: 1022:1482
00:07.0 0600: 1022:1482
00:07.1 0604: 1022:1484
00:08.0 0600: 1022:1482
00:08.1 0604: 1022:1484
00:08.2 0604: 1022:1484
00:08.3 0604: 1022:1484
00:14.0 0c05: 1022:790b (rev 61)
00:14.3 0601: 1022:790e (rev 51)
00:18.0 0600: 1022:1440
00:18.1 0600: 1022:1441
00:18.2 0600: 1022:1442
00:18.3 0600: 1022:1443
00:18.4 0600: 1022:1444
00:18.5 0600: 1022:1445
00:18.6 0600: 1022:1446
00:18.7 0600: 1022:1447
01:00.0 0108: 1987:5016 (rev 01)
02:00.0 0604: 1022:57ad
03:03.0 0604: 1022:57a3
03:05.0 0604: 1022:57a3
03:06.0 0604: 1022:57a3
03:08.0 0604: 1022:57a4
03:09.0 0604: 1022:57a4
03:0a.0 0604: 1022:57a4
04:00.0 0200: 10ec:8125
05:00.0 0200: 8086:1539 (rev 03)
06:00.0 0280: 8086:2723 (rev 1a)
07:00.0 1300: 1022:1485
07:00.1 0c03: 1022:149c
07:00.3 0c03: 1022:149c
08:00.0 0106: 1022:7901 (rev 51)
09:00.0 0106: 1022:7901 (rev 51)
0a:00.0 0300: 10de:1086 (rev a1)
0a:00.1 0403: 10de:0e09 (rev a1)
0b:00.0 1300: 1022:148a
0c:00.0 1300: 1022:1485
0c:00.1 1080: 1022:1486
0c:00.3 0c03: 1022:149c
0c:00.4 0403: 1022:1487
0d:00.0 0106: 1022:7901 (rev 51)
0e:00.0 0106: 1022:7901 (rev 51)
... I'm just finding the same device 00:18.nn which means node 0 and nothing like 00:19.nn up to 00:1F.nn
I don't expect more solution from the PCI enumeration.
- About the CPUID, I'm trying to compute a discriminant from the leave
80000008:00000000
- 3970X : ECX =
0000703fwhere3fmeans 63 + 1 = 64 SMT Cores - 3950X : ECX =
0000701fwhere1fmeans 31 + 1 = 32 SMT Cores
- 3970X : ECX =
To solve a _CCD factor_:
Example| Avail. Cores | SMT | ECX | factor
------------|------------------|--------------|-------|--------
3990X | 64 | 128 | 7f ?| 1
3970X | 32 | 64 | 3f | 2
3960X | 24 | 48 | 2f |2
3950X | 16 | 32 | 1f | 1
3900X | 12 | 24 | 17 | 1
EDIT: dump found at instlatx64
CPUID 80000008: 00003030-018CB757-0000702F-00010000
CPUID 80000008: 00003030-010EB757-00007017-00010000
and then to apply the CCD_factor into the SMU query
Core_AMD_SMN_Read( TccdSensor,
SMU_AMD_THM_TCTL_CCD_REGISTER_F17H
+ (( CCD_factor * Core->T.Cluster.CCD) << 2),
SMU_AMD_INDEX_REGISTER_F17H,
SMU_AMD_DATA_REGISTER_F17H );
I would also like to count the SMU registers by counting the number of UMC
- can you dump the following address
modprobe msr
rdmsr -aX 0x0000017b
- the output of
corefreq-cli -M
rdmsr:
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
FFFFFFFFFFFFFFEF
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
corefreq-cli -M
Zen UMC [1493]
Controller #0 Quad Channel
Bus Rate 0 MT/s Bus Speed 0 MHz DRAM Speed 0 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#1 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#2 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#3 16 15 14 14 32 46 4 6 20 4 12 12 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#1 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#2 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#3 16 8 8 4 1 7 7 1 5 5 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC
#0 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#1 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#2 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#3 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
There should be 2 more memory modules I have actually 4 x 16GB
justanerd
on 7 Sep 2020
There should be 2 more memory modules I have actually 4 x 16GB
Very interesting
- I have the following output from the MSR:
FFFFFFFFFFFFFFEF
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
6F
3950X counts twice the pattern FFFFFFFFFFFFFFEF whereas 3970X , 8 times
- About the UMC, it's still a work in progress.
Thanks for your output, I will check why it does not count 4 DIMMs ?
(_Fyi, to format code in Markdown, place 3 anti-quotes before after the code_)
Zen UMC [1493]
Controller #0 Quad Channel
Bus Rate 0 MT/s Bus Speed 0 MHz DRAM Speed 0 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#1 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#2 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#3 16 15 14 14 32 46 4 6 20 4 12 12 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#1 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#2 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#3 16 8 8 4 1 7 7 1 5 5 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC
#0 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#1 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#2 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#3 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
For the memory module count, I'm refactoring the UMC code. Can you download, compile and run zencli
cc zencli.c -o zencli
# as root:
./zencli umc 0x0
Edit: can you also try the develop branch which has been improved to count the modules and I hope the missing frequency data
The Daemon will output a chips topology I'm interested in.
cyring
on 8 Sep 2020
zencli umc 0x0
Welcome to the Data Fabric: UMC has 0 x Channel(s)
corefreq-cli -M
Zen UMC [1493]
Controller #0 Quad Channel
Bus Rate 0 MT/s Bus Speed 0 MHz DRAM Speed 0 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#1 18 18 18 18 39 57 4 6 26 3 9 18 3 3
#2 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#3 16 15 14 14 32 46 4 6 20 4 12 12 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#1 12 9 5 1 1 3 3 1 3 3 0 0 0 0
#2 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#3 16 8 8 4 1 7 7 1 5 5 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC
#0 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#1 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0
#2 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#3 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
I'm not sure why the timings differ between channel 0,1 and 2,3.
justanerd
on 8 Sep 2020
zencli umc 0x0
Welcome to the Data Fabric: UMC has 0 x Channel(s)corefreq-cli -M
Zen UMC [1493] Controller #0 Quad Channel Bus Rate 0 MT/s Bus Speed 0 MHz DRAM Speed 0 MHz Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW #0 18 18 18 18 39 57 4 6 26 3 9 18 3 3 #1 18 18 18 18 39 57 4 6 26 3 9 18 3 3 #2 16 15 14 14 32 46 4 6 20 4 12 12 4 4 #3 16 15 14 14 32 46 4 6 20 4 12 12 4 4 CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD #0 12 9 5 1 1 3 3 1 3 3 0 0 0 0 #1 12 9 5 1 1 3 3 1 3 3 0 0 0 0 #2 16 8 8 4 1 7 7 1 5 5 0 0 0 0 #3 16 8 8 4 1 7 7 1 5 5 0 0 0 0 REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC #0 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0 #1 9360 312 192 132 0 0 0 0 R0W0 0 6 1T OFF 0 #2 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0 #3 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0 DIMM Geometry for channel #0 Slot Bank Rank Rows Columns Memory Size (MB) #0 #1 2 16 65536 1024 16384 DIMM Geometry for channel #1 Slot Bank Rank Rows Columns Memory Size (MB) #0 #1 2 16 65536 1024 16384 DIMM Geometry for channel #2 Slot Bank Rank Rows Columns Memory Size (MB) #0 #1 2 16 65536 1024 16384 DIMM Geometry for channel #3 Slot Bank Rank Rows Columns Memory Size (MB) #0 #1 2 16 65536 1024 16384I'm not sure why the timings differ between channel 0,1 and 2,3.
Thanks.
As a reference, do you have BIOS screenshots of Timings, or copy them here.
Be aware those registers are undocumented. Sources are Linux kernel for the ECC which includes Chip bits decoding.
I wonder how they got those without AMD !
Timings and Frequency are SMU reversed engineering results spread over the web !
I'm also interested in the corefreqd output you got in terminal.
cyring
on 8 Sep 2020
corefreqd output:
mc[0] cha[0/4] chip[0] sec[0] size[0]
mc[0] cha[0/4] chip[0] sec[1] size[0]
mc[0] cha[0/4] chip[1] sec[0] size[0]
mc[0] cha[0/4] chip[1] sec[1] size[0]
mc[0] cha[0/4] chip[2] sec[0] size[8388608]
mc[0] cha[0/4] chip[2] sec[1] size[0]
mc[0] cha[0/4] chip[3] sec[0] size[8388608]
mc[0] cha[0/4] chip[3] sec[1] size[0]
mc[0] cha[1/4] chip[0] sec[0] size[0]
mc[0] cha[1/4] chip[0] sec[1] size[0]
mc[0] cha[1/4] chip[1] sec[0] size[0]
mc[0] cha[1/4] chip[1] sec[1] size[0]
mc[0] cha[1/4] chip[2] sec[0] size[8388608]
mc[0] cha[1/4] chip[2] sec[1] size[0]
mc[0] cha[1/4] chip[3] sec[0] size[8388608]
mc[0] cha[1/4] chip[3] sec[1] size[0]
mc[0] cha[2/4] chip[0] sec[0] size[0]
mc[0] cha[2/4] chip[0] sec[1] size[0]
mc[0] cha[2/4] chip[1] sec[0] size[0]
mc[0] cha[2/4] chip[1] sec[1] size[0]
mc[0] cha[2/4] chip[2] sec[0] size[8388608]
mc[0] cha[2/4] chip[2] sec[1] size[0]
mc[0] cha[2/4] chip[3] sec[0] size[8388608]
mc[0] cha[2/4] chip[3] sec[1] size[0]
mc[0] cha[3/4] chip[0] sec[0] size[0]
mc[0] cha[3/4] chip[0] sec[1] size[0]
mc[0] cha[3/4] chip[1] sec[0] size[0]
mc[0] cha[3/4] chip[1] sec[1] size[0]
mc[0] cha[3/4] chip[2] sec[0] size[8388608]
mc[0] cha[3/4] chip[2] sec[1] size[0]
mc[0] cha[3/4] chip[3] sec[0] size[8388608]
mc[0] cha[3/4] chip[3] sec[1] size[0]
I will later give you the BIOS screenshots.
justanerd
on 8 Sep 2020
I'm not sure why the timings differ between channel 0,1 and 2,3.
New code available to improve the CCD and SMU _affinity_.
It is available in develop for your Threadripper tests.
Can you post the outputs of the followings:
- the Topology
- the temperature, SMT scope
- the Memory Controller
Thank you
cyring
on 8 Sep 2020
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 131072 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 131072 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 131072 16w
003: 0 6 0 0 3 0 32 8 32 8 512 8 i 131072 16w
004: 0 8 0 1 4 0 32 8 32 8 512 8 i 131072 16w
005: 0 10 0 1 5 0 32 8 32 8 512 8 i 131072 16w
006: 0 12 0 1 6 0 32 8 32 8 512 8 i 131072 16w
007: 0 14 0 1 7 0 32 8 32 8 512 8 i 131072 16w
008: 0 16 2 2 8 0 32 8 32 8 512 8 i 131072 16w
009: 0 18 2 2 9 0 32 8 32 8 512 8 i 131072 16w
010: 0 20 2 2 10 0 32 8 32 8 512 8 i 131072 16w
011: 0 22 2 2 11 0 32 8 32 8 512 8 i 131072 16w
012: 0 24 2 3 12 0 32 8 32 8 512 8 i 131072 16w
013: 0 26 2 3 13 0 32 8 32 8 512 8 i 131072 16w
014: 0 28 2 3 14 0 32 8 32 8 512 8 i 131072 16w
015: 0 30 2 3 15 0 32 8 32 8 512 8 i 131072 16w
016: 0 32 4 4 16 0 32 8 32 8 512 8 i 131072 16w
017: 0 34 4 4 17 0 32 8 32 8 512 8 i 131072 16w
018: 0 36 4 4 18 0 32 8 32 8 512 8 i 131072 16w
019: 0 38 4 4 19 0 32 8 32 8 512 8 i 131072 16w
020: 0 40 4 5 20 0 32 8 32 8 512 8 i 131072 16w
021: 0 42 4 5 21 0 32 8 32 8 512 8 i 131072 16w
022: 0 44 4 5 22 0 32 8 32 8 512 8 i 131072 16w
023: 0 46 4 5 23 0 32 8 32 8 512 8 i 131072 16w
024: 0 48 6 6 24 0 32 8 32 8 512 8 i 131072 16w
025: 0 50 6 6 25 0 32 8 32 8 512 8 i 131072 16w
026: 0 52 6 6 26 0 32 8 32 8 512 8 i 131072 16w
027: 0 54 6 6 27 0 32 8 32 8 512 8 i 131072 16w
028: 0 56 6 7 28 0 32 8 32 8 512 8 i 131072 16w
029: 0 58 6 7 29 0 32 8 32 8 512 8 i 131072 16w
030: 0 60 6 7 30 0 32 8 32 8 512 8 i 131072 16w
031: 0 62 6 7 31 0 32 8 32 8 512 8 i 131072 16w
032: 0 1 0 0 0 1 32 8 32 8 512 8 i 131072 16w
033: 0 3 0 0 1 1 32 8 32 8 512 8 i 131072 16w
034: 0 5 0 0 2 1 32 8 32 8 512 8 i 131072 16w
035: 0 7 0 0 3 1 32 8 32 8 512 8 i 131072 16w
036: 0 9 0 1 4 1 32 8 32 8 512 8 i 131072 16w
037: 0 11 0 1 5 1 32 8 32 8 512 8 i 131072 16w
038: 0 13 0 1 6 1 32 8 32 8 512 8 i 131072 16w
039: 0 15 0 1 7 1 32 8 32 8 512 8 i 131072 16w
040: 0 17 2 2 8 1 32 8 32 8 512 8 i 131072 16w
041: 0 19 2 2 9 1 32 8 32 8 512 8 i 131072 16w
042: 0 21 2 2 10 1 32 8 32 8 512 8 i 131072 16w
043: 0 23 2 2 11 1 32 8 32 8 512 8 i 131072 16w
044: 0 25 2 3 12 1 32 8 32 8 512 8 i 131072 16w
045: 0 27 2 3 13 1 32 8 32 8 512 8 i 131072 16w
046: 0 29 2 3 14 1 32 8 32 8 512 8 i 131072 16w
047: 0 31 2 3 15 1 32 8 32 8 512 8 i 131072 16w
048: 0 33 4 4 16 1 32 8 32 8 512 8 i 131072 16w
049: 0 35 4 4 17 1 32 8 32 8 512 8 i 131072 16w
050: 0 37 4 4 18 1 32 8 32 8 512 8 i 131072 16w
051: 0 39 4 4 19 1 32 8 32 8 512 8 i 131072 16w
052: 0 41 4 5 20 1 32 8 32 8 512 8 i 131072 16w
053: 0 43 4 5 21 1 32 8 32 8 512 8 i 131072 16w
054: 0 45 4 5 22 1 32 8 32 8 512 8 i 131072 16w
055: 0 47 4 5 23 1 32 8 32 8 512 8 i 131072 16w
056: 0 49 6 6 24 1 32 8 32 8 512 8 i 131072 16w
057: 0 51 6 6 25 1 32 8 32 8 512 8 i 131072 16w
058: 0 53 6 6 26 1 32 8 32 8 512 8 i 131072 16w
059: 0 55 6 6 27 1 32 8 32 8 512 8 i 131072 16w
060: 0 57 6 7 28 1 32 8 32 8 512 8 i 131072 16w
061: 0 59 6 7 29 1 32 8 32 8 512 8 i 131072 16w
062: 0 61 6 7 30 1 32 8 32 8 512 8 i 131072 16w
063: 0 63 6 7 31 1 32 8 32 8 512 8 i 131072 16w
Zen UMC [1493]
Controller #0 Dual Channel
Bus Rate 1866 MT/s Bus Speed 1883 MHz DRAM Speed 3767 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#1 16 15 14 14 32 46 4 6 20 4 12 12 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#1 16 8 8 4 1 7 7 1 5 5 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC
#0 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#1 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 2 16 65536 1024 16384
Thank you for providing me all these test results.
- Things look much better. We now have decoded:
- The particular CCD topology of the Threadripper 3970X and consequently the SMU addressing to the temperature sensors and the memory controller.
UMC, DRAM frequencies and timings are showing up.
All of them need to be compared to your BIOS settings.The counting of the 4 x 16GB DIMM is still inaccurate. That is a recurrent issue I'm encountering among Zen processors.
Due to a lack of specifications to blindly code a solution, I will still claim your contribute to code and test differentiate scenarios. Is this OK for you ?
Regards
cyring
on 9 Sep 2020
Sure I'm glad to help.
Any plans to go down this rabbit hole?
https://pbs.twimg.com/media/EhKs3kIXcAMrzjc?format=png&name=small
Would be nice if he releases the source code or at least the PMU documantation or registers for adjusting CCX voltage etc.
justanerd
on 9 Sep 2020
Sure I'm glad to help.
Any plans to go down this rabbit hole?
https://pbs.twimg.com/media/EhKs3kIXcAMrzjc?format=png&name=small
Would be nice if he releases the source code or at least the PMU documantation or registers for adjusting CCX voltage etc.
It brought me to this tweet
Does not look like a FOSS software, although most of those registers addresses are floating on the Internet; guessed by reverse engineering.
Without the BKDG specifications and the voltage usage, we risk to fry the hardware !
At least, I can start with read-only operations
cyring
on 9 Sep 2020
Hello,
- Can you run this updated version of zencli which will scan 16 chips
cc zencli.c -o zencli
# run as root:
./zencli umc 0x0
- _EDIT_: do you have any
SRATorSLITtable in:
/sys/firmware/acpi/tables
Hello,
- Can you run this updated version of zencli which will scan 16 chips
cc zencli.c -o zencli # run as root: ./zencli umc 0x0
Welcome to the Data Fabric: UMC has 2/4 Channels
CHA[0] CHIP[0:0] @ 0x00250000[0x00000000] Disable
CHA[0] MASK[0:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[0:1] @ 0x00250010[0x00000000] Disable
CHA[0] MASK[0:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[0:2] @ 0x00250030[0x00150508] Disable
CHA[0] MASK[0:2] @ 0x00250020[0x00000000]
CHA[0] CHIP[0:3] @ 0x00250040[0x070cba98] Disable
CHA[0] MASK[0:3] @ 0x00250028[0x00000000]
CHA[0] CHIP[1:0] @ 0x00250004[0x00000000] Disable
CHA[0] MASK[1:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[1:1] @ 0x00250014[0x00000000] Disable
CHA[0] MASK[1:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[1:2] @ 0x00250034[0x00150608] Disable
CHA[0] MASK[1:2] @ 0x00250020[0x00000000]
CHA[0] CHIP[1:3] @ 0x00250044[0x060c98ba] Disable
CHA[0] MASK[1:3] @ 0x00250028[0x00000000]
CHA[0] CHIP[2:0] @ 0x00250008[0x00000001] Enable
CHA[0] MASK[2:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[2:1] @ 0x00250018[0x00000000] Disable
CHA[0] MASK[2:1] @ 0x0025002c[0x00000000]
CHA[0] CHIP[2:2] @ 0x00250038[0x00000000] Disable
CHA[0] MASK[2:2] @ 0x00250024[0x03fffdfe]
CHA[0] CHIP[2:3] @ 0x00250048[0x00000000] Disable
CHA[0] MASK[2:3] @ 0x0025002c[0x00000000]
CHA[0] CHIP[3:0] @ 0x0025000c[0x00000201] Enable
CHA[0] MASK[3:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[3:1] @ 0x0025001c[0x00000000] Disable
CHA[0] MASK[3:1] @ 0x0025002c[0x00000000]
CHA[0] CHIP[3:2] @ 0x0025003c[0x00000000] Disable
CHA[0] MASK[3:2] @ 0x00250024[0x03fffdfe]
CHA[0] CHIP[3:3] @ 0x0025004c[0x00000000] Disable
CHA[0] MASK[3:3] @ 0x0025002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
CHA[1] CHIP[0:0] @ 0x00450000[0x00000000] Disable
CHA[1] MASK[0:0] @ 0x00450020[0x00000000]
CHA[1] CHIP[0:1] @ 0x00450010[0x00000000] Disable
CHA[1] MASK[0:1] @ 0x00450028[0x00000000]
CHA[1] CHIP[0:2] @ 0x00450030[0x00150508] Disable
CHA[1] MASK[0:2] @ 0x00450020[0x00000000]
CHA[1] CHIP[0:3] @ 0x00450040[0x070cba98] Disable
CHA[1] MASK[0:3] @ 0x00450028[0x00000000]
CHA[1] CHIP[1:0] @ 0x00450004[0x00000000] Disable
CHA[1] MASK[1:0] @ 0x00450020[0x00000000]
CHA[1] CHIP[1:1] @ 0x00450014[0x00000000] Disable
CHA[1] MASK[1:1] @ 0x00450028[0x00000000]
CHA[1] CHIP[1:2] @ 0x00450034[0x00150608] Disable
CHA[1] MASK[1:2] @ 0x00450020[0x00000000]
CHA[1] CHIP[1:3] @ 0x00450044[0x060c98ba] Disable
CHA[1] MASK[1:3] @ 0x00450028[0x00000000]
CHA[1] CHIP[2:0] @ 0x00450008[0x00000001] Enable
CHA[1] MASK[2:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[2:1] @ 0x00450018[0x00000000] Disable
CHA[1] MASK[2:1] @ 0x0045002c[0x00000000]
CHA[1] CHIP[2:2] @ 0x00450038[0x00000000] Disable
CHA[1] MASK[2:2] @ 0x00450024[0x03fffdfe]
CHA[1] CHIP[2:3] @ 0x00450048[0x00000000] Disable
CHA[1] MASK[2:3] @ 0x0045002c[0x00000000]
CHA[1] CHIP[3:0] @ 0x0045000c[0x00000201] Enable
CHA[1] MASK[3:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[3:1] @ 0x0045001c[0x00000000] Disable
CHA[1] MASK[3:1] @ 0x0045002c[0x00000000]
CHA[1] CHIP[3:2] @ 0x0045003c[0x00000000] Disable
CHA[1] MASK[3:2] @ 0x00450024[0x03fffdfe]
CHA[1] CHIP[3:3] @ 0x0045004c[0x00000000] Disable
CHA[1] MASK[3:3] @ 0x0045002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
- _EDIT_: do you have any
SRATorSLITtable in:/sys/firmware/acpi/tablesyes
justanerd
on 10 Sep 2020
- zencli updated : can you download and run it again ?
cyring
on 10 Sep 2020
Data Fabric: scanning UMC 0 2 4 6 for 2/4 Channels
CHA[0] CHIP[0:0] @ 0x00250000[0x00000000] Disable
CHA[0] MASK[0:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[0:1] @ 0x00250010[0x00000000] Disable
CHA[0] MASK[0:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[1:0] @ 0x00250004[0x00000000] Disable
CHA[0] MASK[1:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[1:1] @ 0x00250014[0x00000000] Disable
CHA[0] MASK[1:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[2:0] @ 0x00250008[0x00000001] Enable
CHA[0] MASK[2:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[2:1] @ 0x00250018[0x00000000] Disable
CHA[0] MASK[2:1] @ 0x0025002c[0x00000000]
CHA[0] CHIP[3:0] @ 0x0025000c[0x00000201] Enable
CHA[0] MASK[3:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[3:1] @ 0x0025001c[0x00000000] Disable
CHA[0] MASK[3:1] @ 0x0025002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
CHA[1] CHIP[0:0] @ 0x00450000[0x00000000] Disable
CHA[1] MASK[0:0] @ 0x00450020[0x00000000]
CHA[1] CHIP[0:1] @ 0x00450010[0x00000000] Disable
CHA[1] MASK[0:1] @ 0x00450028[0x00000000]
CHA[1] CHIP[1:0] @ 0x00450004[0x00000000] Disable
CHA[1] MASK[1:0] @ 0x00450020[0x00000000]
CHA[1] CHIP[1:1] @ 0x00450014[0x00000000] Disable
CHA[1] MASK[1:1] @ 0x00450028[0x00000000]
CHA[1] CHIP[2:0] @ 0x00450008[0x00000001] Enable
CHA[1] MASK[2:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[2:1] @ 0x00450018[0x00000000] Disable
CHA[1] MASK[2:1] @ 0x0045002c[0x00000000]
CHA[1] CHIP[3:0] @ 0x0045000c[0x00000201] Enable
CHA[1] MASK[3:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[3:1] @ 0x0045001c[0x00000000] Disable
CHA[1] MASK[3:1] @ 0x0045002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
- Can you please try this loop:
for addr in 0x050104 0x150104 0x250104 0x350104 0x450104 0x550104 0x650104 0x750104; do echo -n "${addr}: "; ./zencli smu ${addr}; done
0x050104: 0x30408088 (809533576)
0x150104: 0x30408088 (809533576)
0x250104: 0xb040808b (2957017227)
0x350104: 0xb040808b (2957017227)
0x450104: 0xb040808b (2957017227)
0x550104: 0xb040808b (2957017227)
0x650104: 0x30408088 (809533576)
0x750104: 0x30408088 (809533576)
0x050104: 0x30408088 (809533576) 0x150104: 0x30408088 (809533576) 0x250104: 0xb040808b (2957017227) 0x350104: 0xb040808b (2957017227) 0x450104: 0xb040808b (2957017227) 0x550104: 0xb040808b (2957017227) 0x650104: 0x30408088 (809533576) 0x750104: 0x30408088 (809533576)
Very instructive: different from the CCD interlaced temperature sensor registers
cyring
on 10 Sep 2020
- zencli once again updated, can you give it a try ?
./zencli umc 0x0
Data Fabric: scanning UMC 0 1 2 3 4 5 6 7 for 4 Channels
CHA[0] CHIP[0:0] @ 0x00250000[0x00000000] Disable
CHA[0] MASK[0:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[0:1] @ 0x00250010[0x00000000] Disable
CHA[0] MASK[0:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[1:0] @ 0x00250004[0x00000000] Disable
CHA[0] MASK[1:0] @ 0x00250020[0x00000000]
CHA[0] CHIP[1:1] @ 0x00250014[0x00000000] Disable
CHA[0] MASK[1:1] @ 0x00250028[0x00000000]
CHA[0] CHIP[2:0] @ 0x00250008[0x00000001] Enable
CHA[0] MASK[2:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[2:1] @ 0x00250018[0x00000000] Disable
CHA[0] MASK[2:1] @ 0x0025002c[0x00000000]
CHA[0] CHIP[3:0] @ 0x0025000c[0x00000201] Enable
CHA[0] MASK[3:0] @ 0x00250024[0x03fffdfe] ChipSize[8388608]
CHA[0] CHIP[3:1] @ 0x0025001c[0x00000000] Disable
CHA[0] MASK[3:1] @ 0x0025002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
CHA[1] CHIP[0:0] @ 0x00350000[0x00000000] Disable
CHA[1] MASK[0:0] @ 0x00350020[0x00000000]
CHA[1] CHIP[0:1] @ 0x00350010[0x00000000] Disable
CHA[1] MASK[0:1] @ 0x00350028[0x00000000]
CHA[1] CHIP[1:0] @ 0x00350004[0x00000000] Disable
CHA[1] MASK[1:0] @ 0x00350020[0x00000000]
CHA[1] CHIP[1:1] @ 0x00350014[0x00000000] Disable
CHA[1] MASK[1:1] @ 0x00350028[0x00000000]
CHA[1] CHIP[2:0] @ 0x00350008[0x00000001] Enable
CHA[1] MASK[2:0] @ 0x00350024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[2:1] @ 0x00350018[0x00000000] Disable
CHA[1] MASK[2:1] @ 0x0035002c[0x00000000]
CHA[1] CHIP[3:0] @ 0x0035000c[0x00000201] Enable
CHA[1] MASK[3:0] @ 0x00350024[0x03fffdfe] ChipSize[8388608]
CHA[1] CHIP[3:1] @ 0x0035001c[0x00000000] Disable
CHA[1] MASK[3:1] @ 0x0035002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
CHA[2] CHIP[0:0] @ 0x00450000[0x00000000] Disable
CHA[2] MASK[0:0] @ 0x00450020[0x00000000]
CHA[2] CHIP[0:1] @ 0x00450010[0x00000000] Disable
CHA[2] MASK[0:1] @ 0x00450028[0x00000000]
CHA[2] CHIP[1:0] @ 0x00450004[0x00000000] Disable
CHA[2] MASK[1:0] @ 0x00450020[0x00000000]
CHA[2] CHIP[1:1] @ 0x00450014[0x00000000] Disable
CHA[2] MASK[1:1] @ 0x00450028[0x00000000]
CHA[2] CHIP[2:0] @ 0x00450008[0x00000001] Enable
CHA[2] MASK[2:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[2] CHIP[2:1] @ 0x00450018[0x00000000] Disable
CHA[2] MASK[2:1] @ 0x0045002c[0x00000000]
CHA[2] CHIP[3:0] @ 0x0045000c[0x00000201] Enable
CHA[2] MASK[3:0] @ 0x00450024[0x03fffdfe] ChipSize[8388608]
CHA[2] CHIP[3:1] @ 0x0045001c[0x00000000] Disable
CHA[2] MASK[3:1] @ 0x0045002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
CHA[3] CHIP[0:0] @ 0x00550000[0x00000000] Disable
CHA[3] MASK[0:0] @ 0x00550020[0x00000000]
CHA[3] CHIP[0:1] @ 0x00550010[0x00000000] Disable
CHA[3] MASK[0:1] @ 0x00550028[0x00000000]
CHA[3] CHIP[1:0] @ 0x00550004[0x00000000] Disable
CHA[3] MASK[1:0] @ 0x00550020[0x00000000]
CHA[3] CHIP[1:1] @ 0x00550014[0x00000000] Disable
CHA[3] MASK[1:1] @ 0x00550028[0x00000000]
CHA[3] CHIP[2:0] @ 0x00550008[0x00000001] Enable
CHA[3] MASK[2:0] @ 0x00550024[0x03fffdfe] ChipSize[8388608]
CHA[3] CHIP[2:1] @ 0x00550018[0x00000000] Disable
CHA[3] MASK[2:1] @ 0x0055002c[0x00000000]
CHA[3] CHIP[3:0] @ 0x0055000c[0x00000201] Enable
CHA[3] MASK[3:0] @ 0x00550024[0x03fffdfe] ChipSize[8388608]
CHA[3] CHIP[3:1] @ 0x0055001c[0x00000000] Disable
CHA[3] MASK[3:1] @ 0x0055002c[0x00000000]
DIMM Size[16777216 KB] [16384 MB]
Yes ! this time we found your 4 sticks of 16 GB
I will update _CoreFreq_
cyring
on 10 Sep 2020
- The
developbranch is updated for your UMC testings. Thank you.
cyring
on 10 Sep 2020
Looks good the timing should also be ok .
Zen UMC [1493]
Controller #0 Quad Channel
Bus Rate 1866 MT/s Bus Speed 1883 MHz DRAM Speed 3767 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#1 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#2 16 15 14 14 32 46 4 6 20 4 12 12 4 4
#3 16 15 14 14 32 46 4 6 20 4 12 12 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#1 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#2 16 8 8 4 1 7 7 1 5 5 0 0 0 0
#3 16 8 8 4 1 7 7 1 5 5 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB sFAW dFAW Ban Page CKE CMD GDM ECC
#0 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#1 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#2 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
#3 14553 298 192 132 0 0 0 0 R1W1 0 1 1T ON 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
DIMM Geometry for channel #2
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
DIMM Geometry for channel #3
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 65536 1024 16384
Thank you for your patience. Glade of the results.
I'm copying those results to the main UMC issue #196
Feel free to switch to it.
cyring
on 10 Sep 2020
Hello,
The _CoreFreq_ CPU-IDLE is available for your tests in the develop branch
- It registers the following idle states (which are a copy of my ACPI values)
https://github.com/cyring/CoreFreq/blob/e4da673f586a0d59fc1a4c7ace106ee02a24ba46/corefreqk.h#L4569 - Kernel will be asked to invoke the following handler (which should executes an
MWAITat the end)
https://github.com/cyring/CoreFreq/blob/e4da673f586a0d59fc1a4c7ace106ee02a24ba46/corefreqk.c#L11294
See starting instructions in https://github.com/cyring/CoreFreq/issues/115#issuecomment-699469580
So far, it has been with tested with my 3950 Matisse. Waking from idle is stable up to now.
Any additional tests with Zen, first generations, are welcomed because I suspect a
MWAITbug according to AMD errata. In that case, I will implement aHALThandler for those models.
cyring
on 26 Sep 2020
Neat. So CoreFreq might work on TRX40 (my 3960X)? I could test it out.
Chlorophytus
on 15 Oct 2020
Neat. So CoreFreq might work on TRX40 (my 3960X)? I could test it out.
Yes, it's running.
- Latest in
developbranch forMWAITlatency and residency tuning where you can tune values at these lines:
https://github.com/cyring/CoreFreq/blob/002e04ff0eb5af284c8e61e24e0a04b535b6470f/corefreqk.h#L4779
Let me know what's the best values for your architecture (or if current is fine)
Don't forget to fully rebuild and reload driver each time you change the header file.
At exit, the Cli will prompt you to unregister the
IDLEsub-driver (or you won't be able unload the _CoreFreq_ driver)
cyring
on 15 Oct 2020
hello
Does anybody see boost frequencies on the cpu? I am unable to reach them (BIOS with factory default, windows does use boost normally).
I have tried all the recommendations on this thread, with three different kernels (5.10.0-rc4 5.4.77 5.9.8). I have also used the recommended linux parameters to disable the linux provided governor, etc, and I have activated the corefreq ones.
Thanks a lot!
PD: how did you achieved a 400MHz minimum MHz? what's the power consumption on idle on that situation?
gdiazlo
on 18 Nov 2020
hello
Does anybody see boost frequencies on the cpu? I am unable to reach them (BIOS with factory default, windows does use boost normally).
I have tried all the recommendations on this thread, with three different kernels (5.10.0-rc4 5.4.77 5.9.8). I have also used the recommended linux parameters to disable the linux provided governor, etc, and I have activated the corefreq ones.
Hello,
Just to share with you how I'm triggering Turbo in _CoreFreq_, I have recorded this demo:
https://asciinema.org/a/9wakosVIpU7vPle6py5c6hLTR
Please notice:
- my development setup is a 3950X, thus Matisse architecture. #199
- currently using Arch kernel
5.9.8
Before jumping into my experimental CPU-Idle and CPU-Freq sub-drivers, we will rely on the mainstream drivers: acpi_idle , acpi-cpufreq , schedutil to trigger Turbo.
So please just build and start _CoreFreq_ the simple way:
make clean all
## as root
insmod corefreqk.ko
./corefreqd -q
## as a user
./corefreq-cli
Now we will trigger Turbo using the integrated stress loops:
Press [O] for Tools > Turbo < Select CPU > and select your best Core. Mine is CPU #0
Press [F10] at any time to stop stressing.
Q: At this point, was Turbo triggered ?
Thanks a lot!
...
PD: how did you achieved a 400MHz minimum MHz? what's the power consumption on idle on that situation?
For your information, 2 measurements are available:
- Relative frequency
- Absolute frequency
You toggle the measurement mode by pressing shortcut [!]
Relative is the usage of the CPU over the sampling period whereas Absolute is the frequency ratio collected at each period tick.
If Absolute shows the 3970X expected Turbo ratio but not Relative, it would mean I have a querying issue with the Performance counters on Castle Peak.
Those performance counters UCC , URC can also be shown in the View > Core cycles (or shortcut [c])
Please let me about those test results before going further in the issue.
Regards
CyrIng
cyring
on 18 Nov 2020
Wow I tried the steps you demonstrated on the video and all I can get is around 4.5GHz. We have similar hardware with same motherboard and CPU. The only difference is the RAM which mine is the Flare X 3200 CL14 kit (4x 8Gb). I am thinking the Ryzen 3000 series can't handle the 4x DIMM slots as good as the 2x DIMM slots.
inglor
on 18 Nov 2020
Wow I tried the steps you demonstrated on the video and all I can get is around 4.5GHz.
Were you expecting more than the 3970X Boost specification ?
We have similar hardware with same motherboard and CPU. The only difference is the RAM which mine is the Flare X 3200 CL14 kit (4x 8Gb). I am thinking the Ryzen 3000 series can't handle the 4x DIMM slots as good as the 2x DIMM slots.
Differences appears more than that. Press [m] for the Core topology. Some CCD/CCX might be more perf than others.
DRAM affinity with Cores cluster may also impacts perf.
AMD is publishing documents for code micro-optimizations. Links in _CoreFreq_ wiki.
cyring
on 18 Nov 2020
With the settings you mentioned, with kernels 5.10.0-rc4 and 5.9.8 I am unable to see Core Boost. The BIOS is on its defaults, the only modification is the memory profile which is loaded (ddr4 3600 instead of the default).
On your video I see when turbo activates it marks more than 100%, but I don't see that. It marks 100%.
I suspect this parameter should be 4500000 or whatever, but its default value is
(develop)$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3700000
and I am unable to change it. boost and cpb are enabled.
gdiazlo
on 18 Nov 2020
Wow I tried the steps you demonstrated on the video and all I can get is around 4.5GHz.
Were you expecting more than the 3970X Boost specification ?
We have similar hardware with same motherboard and CPU. The only difference is the RAM which mine is the Flare X 3200 CL14 kit (4x 8Gb). I am thinking the Ryzen 3000 series can't handle the 4x DIMM slots as good as the 2x DIMM slots.
Differences appears more than that. Press
[m]for the Core topology. Some CCD/CCX might be more perf than others.
DRAM affinity with Cores cluster may also impacts perf.
AMD is publishing documents for code micro-optimizations. Links in _CoreFreq_ wiki.
I think you are confused - it's actually my fault though since I highjacked this thread - I'll make a new thread.
inglor
on 18 Nov 2020
With the settings you mentioned, with kernels 5.10.0-rc4 and 5.9.8 I am unable to see Core Boost. The BIOS is on its defaults, the only modification is the memory profile which is loaded (ddr4 3600 instead of the default).
On your video I see when turbo activates it marks more than 100%, but I don't see that. It marks 100%.
I suspect this parameter should be 4500000 or whatever, but its default value is
(develop)$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
3700000and I am unable to change it. boost and cpb are enabled.
2 new things for me in your screenshot:
- Kernel 5.10
- Taichi
- So far, no regression encountered among kernel versions.
- Threadripper Zen2: at least one user reported it's working _fine_
- Asrock Taichi: it is the first time I can see _CoreFreq_ running with it.
Does the Taichi allow Boost differently than the Asus boards ?
The scalling ratio returned by the Kernel module: are the ACPI settings fully enabled in BIOS ?
cyring
on 19 Nov 2020
I tried kernel 5.9.8 with the exact same results. The BIOS is in its default settings, so everything is set to auto.
During boot I discovered these messages (in 5.10.0-rc4 and in 5.9.8) I am going to try an older kernel 5.4.xx and see if the ACPI errors are there.
[ 1.681588] ACPI: Added _OSI(Module Device)
[ 1.681588] ACPI: Added _OSI(Processor Device)
[ 1.681589] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 1.681589] ACPI: Added _OSI(Processor Aggregator Device)
[ 1.681590] ACPI: Added _OSI(Linux-Dell-Video)
[ 1.681591] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[ 1.681591] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[ 1.693332] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.WT1A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693336] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693337] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693339] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.MT1A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693341] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693342] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693343] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.WT2A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693344] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693345] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693347] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.MT2A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693348] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693349] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693350] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.WT3A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693352] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693353] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693354] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.MT3A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693355] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693356] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693358] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.WT4A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693359] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693360] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693361] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.MT4A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693363] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693364] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693365] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CA.MT5A], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693366] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693367] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693370] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CB.WT1B], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693371] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693372] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693373] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CB.MT1B], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693375] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693376] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693377] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CB.WT2B], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693378] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693379] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693380] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CB.MT2B], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693382] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693383] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
....
[ 1.693459] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693460] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CD.WT4D], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693461] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693462] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693463] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CD.MT4D], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693465] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693466] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693467] ACPI BIOS Error (bug): Failure creating named object [\_SB.I2CD.MT5D], AE_ALREADY_EXISTS (20200925/dswload2-326)
[ 1.693469] ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-220)
[ 1.693470] ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x5B82)
[ 1.693534] ACPI: 8 ACPI AML tables successfully acquired and loaded
[ 1.697377] ACPI: Interpreter enabled
[ 1.697387] ACPI: (supports S0 S3 S4 S5)
[ 1.697388] ACPI: Using IOAPIC for interrupt routing
[ 1.697581] PCI: MMCONFIG for domain 0000 [bus 00-7f] at [mem 0xf0000000-0xf7ffffff] (base 0xf0000000)
[ 1.697609] PCI: MMCONFIG at [mem 0xf0000000-0xf7ffffff] reserved in ACPI motherboard resources
[ 1.697616] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 1.697977] ACPI: Enabled 3 GPEs in block 00 to 1F
[ 1.709561] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-1f])
I tried kernel 5.9.8 with the exact same results. The BIOS is in its default settings, so everything is set to auto.
During boot I discovered these messages (in 5.10.0-rc4 and in 5.9.8) I am going to try an older kernel 5.4.xx and see if the ACPI errors are there.
- Nominal case is reporting those logs with my system #199
(addresses masked on purpose)
dmesg -t|grep -i acpi
...
BIOS-e820: [mem 0x00000000ZZZZZZZZ-0x00000000ZZZZZZZZ] ACPI NVS
BIOS-e820: [mem 0x00000000ZZZZZZZZ-0x00000000ZZZZZZZZ] ACPI data
BIOS-e820: [mem 0x00000000ZZZZZZZZ-0x00000000ZZZZZZZZ] ACPI NVS
efi: ACPI=0xZZZZZZZZ ACPI 2.0=0xZZZZZZZZ SMBIOS=0xZZZZZZZZ SMBIOS 3.0=0xZZZZZZZZ MEMATTR=0xZZZZZZZZ ESRT=0xZZZZZZZZ RNG=0xZZZZZZZZ
ACPI: Early table checksum verification disabled
ACPI: RSDP 0x00000000ZZZZZZZZ 000024 (v02 ALASKA)
ACPI: XSDT 0x00000000ZZZZZZZZ 0000BC (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: FACP 0x00000000ZZZZZZZZ 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
ACPI: DSDT 0x00000000ZZZZZZZZ 00E430 (v02 ALASKA A M I 01072009 INTL 20120913)
ACPI: FACS 0x00000000ZZZZZZZZ 000040
ACPI: SSDT 0x00000000ZZZZZZZZ 008C98 (v02 AMD AmdTable 00000002 MSFT 04000000)
ACPI: SSDT 0x00000000ZZZZZZZZ 003ACB (v01 AMD AMD AOD 00000001 INTL 20120913)
ACPI: SSDT 0x00000000ZZZZZZZZ 0001CC (v02 ALASKA CPUSSDT 01072009 AMI 01072009)
ACPI: FIDT 0x00000000ZZZZZZZZ 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: FPDT 0x00000000ZZZZZZZZ 000044 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: MCFG 0x00000000ZZZZZZZZ 00003C (v01 ALASKA A M I 01072009 MSFT 00010013)
ACPI: HPET 0x00000000ZZZZZZZZ 000038 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: SSDT 0x00000000ZZZZZZZZ 000024 (v01 AMD BIXBY 00001000 INTL 20120913)
ACPI: IVRS 0x00000000ZZZZZZZZ 0000D0 (v02 AMD AmdTable 00000001 AMD 00000000)
ACPI: PCCT 0x00000000ZZZZZZZZ 00006E (v02 AMD AmdTable 00000001 AMD 00000000)
ACPI: SSDT 0x00000000ZZZZZZZZ 007D49 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: CRAT 0x00000000ZZZZZZZZ 001D58 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: CDIT 0x00000000ZZZZZZZZ 000029 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000ZZZZZZZZ 00022A (v01 AMD QOGIRDGP 00000001 INTL 20120913)
ACPI: SSDT 0x00000000ZZZZZZZZ 003445 (v01 AMD QOGIRN 00000001 INTL 20120913)
ACPI: WSMT 0x00000000ZZZZZZZZ 000028 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: APIC 0x00000000ZZZZZZZZ 00015E (v03 ALASKA A M I 01072009 AMI 00010013)
ACPI: SSDT 0x00000000ZZZZZZZZ 0010AF (v01 AMD QOGIRC 00000001 INTL 20120913)
ACPI: Local APIC address 0xfee00000
ACPI: PM-Timer IO Port: 0x808
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
ACPI: IRQ0 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information
ACPI: HPET id: 0x10228201 base: 0xfed00000
ACPI: Core revision 20200717
PM: Registering ACPI NVS region [mem 0x00000000ZZZZZZZZ-0x00000000ZZZZZZZZ] (65536 bytes)
PM: Registering ACPI NVS region [mem 0x00000000ZZZZZZZZ-0x00000000ZZZZZZZZ] (7159808 bytes)
ACPI: bus type PCI registered
acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
ACPI: Added _OSI(Module Device)
ACPI: Added _OSI(Processor Device)
ACPI: Added _OSI(3.0 _SCP Extensions)
ACPI: Added _OSI(Processor Aggregator Device)
ACPI: Added _OSI(Linux-Dell-Video)
ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
ACPI: 9 ACPI AML tables successfully acquired and loaded
ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
ACPI: EC: EC started
ACPI: EC: interrupt blocked
ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
ACPI: \_SB_.PCI0.SBRG.EC0_: Boot DSDT EC used to handle transactions
ACPI: Interpreter enabled
ACPI: (supports S0 S3 S4 S5)
ACPI: Using IOAPIC for interrupt routing
PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
ACPI: Enabled 2 GPEs in block 00 to 1F
ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3]
acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug LTR DPC]
acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-7f] only partially covers this bridge
ACPI: PCI Interrupt Link [LNKA] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKB] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKC] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKD] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKE] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKF] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKG] (IRQs 4 5 7 10 11 14 15) *0
ACPI: PCI Interrupt Link [LNKH] (IRQs 4 5 7 10 11 14 15) *0
ACPI: EC: interrupt unblocked
ACPI: EC: event unblocked
ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
ACPI: EC: GPE=0x2
ACPI: \_SB_.PCI0.SBRG.EC0_: Boot DSDT EC initialization complete
ACPI: \_SB_.PCI0.SBRG.EC0_: EC: Used to handle transactions and events
ACPI: bus type USB registered
PCI: Using ACPI for IRQ routing
pnp: PnP ACPI init
system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
pnp: PnP ACPI: found 5 devices
...
ACPI: Power Button [PWRB]
ACPI: Power Button [PWRF]
ACPI: \_PR_.C000: Found 2 idle states
ACPI: \_PR_.C002: Found 2 idle states
ACPI: \_PR_.C004: Found 2 idle states
ACPI: \_PR_.C006: Found 2 idle states
ACPI: \_PR_.C008: Found 2 idle states
ACPI: \_PR_.C00A: Found 2 idle states
ACPI: \_PR_.C00C: Found 2 idle states
ACPI: \_PR_.C00E: Found 2 idle states
ACPI: \_PR_.C010: Found 2 idle states
ACPI: \_PR_.C012: Found 2 idle states
ACPI: \_PR_.C014: Found 2 idle states
ACPI: \_PR_.C016: Found 2 idle states
ACPI: \_PR_.C018: Found 2 idle states
ACPI: \_PR_.C01A: Found 2 idle states
ACPI: \_PR_.C01C: Found 2 idle states
ACPI: \_PR_.C01E: Found 2 idle states
ACPI: \_PR_.C001: Found 2 idle states
ACPI: \_PR_.C003: Found 2 idle states
ACPI: \_PR_.C005: Found 2 idle states
ACPI: \_PR_.C007: Found 2 idle states
ACPI: \_PR_.C009: Found 2 idle states
ACPI: \_PR_.C00B: Found 2 idle states
ACPI: \_PR_.C00D: Found 2 idle states
ACPI: \_PR_.C00F: Found 2 idle states
ACPI: \_PR_.C011: Found 2 idle states
ACPI: \_PR_.C013: Found 2 idle states
ACPI: \_PR_.C015: Found 2 idle states
ACPI: \_PR_.C017: Found 2 idle states
ACPI: \_PR_.C019: Found 2 idle states
ACPI: \_PR_.C01B: Found 2 idle states
ACPI: \_PR_.C01D: Found 2 idle states
ACPI: \_PR_.C01F: Found 2 idle states
acpi_cpufreq: overriding BIOS provided _PSD data
acpi PNP0C14:02: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:01)
acpi PNP0C14:03: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:01)
acpi PNP0C14:04: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:01)
acpi PNP0C14:05: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:01)
As you can notice, the ACPI tables and the idle States are _correctly_ acquired by the Kernel version
5.9.8based on ArchLinuxSome parameters I have added into the boot command line
initrd=\EFI\Linux\amd-ucode.img initrd=\EFI\Linux\initramfs-linux.img root=/dev/disk/by-label/root rw quiet break=n add_efi_memmap nmi_watchdog=0 selinux=0 modprobe.blacklist=nouveau,pcspkr,k10temp,sp5100_tco cpu0_hotplug audit=0 nowatchdog sysrq_always_enabled
I have downgraded the BIOS of the motherboard to version 1.1, with an older AGESA. Now I can reach turbo speeds.
Still, the ACPI messages are very simmilar with kernel 5.9.8 and 5.10.0-rc4, any ideas on what to look to see what was changed in the BIOS for this to happen?
On windows, with the recent bioses, I could instruct Ryzen Master to reset the CPU to its default parameters and the core boost frequencies startes working, but I don't know how to do that on linux.
The kernel parameters I've used are (based on what you have):
BOOT_IMAGE=dev001:\EFI\Slackware\vmlinuz root=/dev/sdb2 ro vt.global_cursor_default=0 quiet loglevel=3 vga=current logo.nologo break=n add_efi_memmap nmi_watchdog=0 modprobe.blacklist=nouveau,pcspkr,k10temp,sp5100_tcocpu0_hotplug audit=0 nowatchdog sysreq_always_enabled ro
I'm happy to see you're getting Turbo back again.
Ryzen Master can do things because, as an AMD product, it has the privilege to access the NDA specifications.
Linux and _CoreFreq_, we just have so far a limited overview of the Zen registers
EDIT. Fyi, you can scroll into the Monitoring view with the Up and Down arrow keys, when no window opened, or Minus and Plus keys in any other case.
cyring
on 19 Nov 2020
Can you plz show me the _CoreFreq_ Memory Controller output ?
cyring
on 20 Nov 2020
I have installed an archilinux on the machine to do tets with the other BIOSs and see if I can get it to work.
Here is the memory controller section:
thanks for the tip of scrolling! :)
gdiazlo
on 20 Nov 2020
I have installed an archilinux on the machine to do tets with the other BIOSs and see if I can get it to work.
Here is the memory controller section:
...
thanks for the tip of scrolling! :)
Thank you for your screenshot, please let me know if values differ from your BIOS ?
Could you also help me to check if the CPB, XFR ratios can be correctly queried on Castle Peak ?
You will have to replace those source code lines at:
https://github.com/cyring/CoreFreq/blob/b92bcd6ae8ca57828087ee97fdc2544e250d539d/corefreqk.h#L4013
with these lines:
{
.Brand = ZLIST("AMD Ryzen Threadripper 3970X"),
.Boost = {0, 0},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_CASTLE_PEAK,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK
},
Next rebuild and restart all _CoreFreq_ and post the output of the Client as below
make clean all
insmod corefreqk.ko
./corefreqd
./corefreq-cli -s
Thank you
cyring
on 21 Nov 2020
Sure, here it is the data :) (boost is disabled on the acpi driver on this tests btw)
```
(develop)$ ./corefreq-cli -s
Processor [AMD Ryzen Threadripper 3970X 32-Core Processor]
|- Architecture [Zen2/Castle Peak]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x08301025]
|- Signature [ 8F_31]
|- Stepping [ 0]
|- Online CPU [ 64/ 64]
|- Base Clock [ 99.999]
|- Frequency (MHz) Ratio
Min 2199.97 < 22 >
Max 3699.95 < 37 >
|- Factory [100.000]
3700 [ 37 ]
|- Performance
|- P-State
TGT 3699.95 < 37 >
|- Turbo Boost [ UNLOCK]
1C 2799.96 < 28 >
2C 2199.97 < 22 >
|- Uncore [ LOCK]
Min 1799.98 [ 18 ]
Max 1799.98 [ 18 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH/O [Y/Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Missing]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
Technologies
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E
|- C2 UnDemotion C2U
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x813 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Performance Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power & Thermal
|- Clock Modulation ODCM [Disable]
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP [ 0]
|- Junction Temperature TjMax [ 49: 12]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [Capable]
|- Thermal Monitor 2 HTC [Capable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562
````
gdiazlo
on 21 Nov 2020
Sure, here it is the data :) (boost is disabled on the acpi driver on this tests btw)
|- Turbo Boost [ UNLOCK] 1C 2799.96 < 28 > 2C 2199.97 < 22 > Technologies |- Core Performance Boost CPB < ON>
Thank you for you test.
But I have an issue: CPB is detected as enabled but CPB and XFR ratios are not showing up in the Turbo list. Which means that the undocumented register I'm using for Castle Peak has returned zero.
Do you mind to try with the Matisse register ?
- Still keeping the earlier change made in corefreqk.h
- Please replace the statement at line:
https://github.com/cyring/CoreFreq/blob/b92bcd6ae8ca57828087ee97fdc2544e250d539d/corefreqk.c#L5115
with:
case AMD_Zen2_CPK:
Core_AMD_SMN_Read(XtraCOF,
SMU_AMD_F17H_MATISSE_COF,
SMU_AMD_INDEX_REGISTER_F17H,
SMU_AMD_DATA_REGISTER_F17H);
break;
I have disabled the boost using the acpi driver...may be that's doing domething in this case. Any way here, here is the output after testing :)
(develop)$ ./corefreq-cli -s
Processor [AMD Ryzen Threadripper 3970X 32-Core Processor]
|- Architecture [Zen2/Castle Peak]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x08301025]
|- Signature [ 8F_31]
|- Stepping [ 0]
|- Online CPU [ 64/ 64]
|- Base Clock [ 99.998]
|- Frequency (MHz) Ratio
Min 2199.96 < 22 >
Max 3699.94 < 37 >
|- Factory [100.000]
3700 [ 37 ]
|- Performance
|- P-State
TGT 2800.01 < 28 >
|- Turbo Boost [ UNLOCK]
1C 2799.95 < 28 >
2C 2199.96 < 22 >
|- Uncore [ LOCK]
Min 1799.97 [ 18 ]
Max 1799.97 [ 18 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH/O [Y/Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Missing]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
Technologies
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U <OFF>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x813 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Performance Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power & Thermal
|- Clock Modulation ODCM [Disable]
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP [ 0]
|- Junction Temperature TjMax [ 49: 12]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [Capable]
|- Thermal Monitor 2 HTC [Capable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
I have disabled the boost using the acpi driver...may be that's doing domething in this case. Any way here, here is the output after testing :)
|- Core Performance Boost CPB < ON>
That's indeed the issue. The driver has not detected the Boost state change.
I'm not aware of other methods to disable Boost beside clearing its register bit.
Can you post the commands or parameters used in acpi_cpufreq ?
cyring
on 22 Nov 2020
I just did
````
echo 0 > /sys/devices/system/cpu/cpufreq/boost
````
I do this to use BOINC, because with air cooling and core boost, the CPU gets too hot for too many hours for my tastes. I hope to get better cooling soon :)
gdiazlo
on 22 Nov 2020
echo 0 > /sys/devices/system/cpu/cpufreq/boost
It goes unsynchronized. I need to check what acpi-cpufreq is doing.
- When using _CoreFreq_ you will disable Boost from the UI in the Technologies window or straight from the driver using argument
TurboBoost_Enable - Boost disabled
insmod corefreqk.ko TurboBoost_Enable=0
- Boost enabled
insmod corefreqk.ko TurboBoost_Enable=1
- If you are in need of the CPU-Freq framework (because of the
/sys/devices/system/cpu/cpufreq/*files) then you have to register _CoreFreq_ as the sole CPU-Freq driver. See Q&R in README.md about blacklistingacpi-cpufreqand kernel boot options prerequisites.
corefreq-cli -kconfirms which are the current CPU-Freq driver and governor.
About the test, could you execute it without touching Boost, making sure it is enabled.
Rollback the changes incorefreqk.cbut keep changescorefreqk.hThe purpose of this test is to check if the _CoreFreq_ driver is able to query the Boost ratios from the SMU registers on Castle Peak. It implies that CPB has to be activated.
Thank you.
EDIT:
- At any time, in the UI, you can press the
*to request a refresh. - I have checked that it's working fine when _CoreFreq_ is registered as the CPU-Freq driver + governor and the Boost is toggled from
/sys/devices/system/cpu/cpufreq/boost: the state is automatically reflected into the BOOST tag of footer and in the Technologies window.
Fyi CPU-Freq driver arguments are:
insmod corefreqk.ko Register_Governor=1 Register_CPU_Freq=1
Kernel boot options will be:
modprobe.blacklist=acpi_cpufreq
To use _CoreFreq_ Idle-SubDriver
insmod corefreqk.ko Register_CPU_Idle=1 Register_ClockSource=1
and add these to kernel
idle=halt tsc=unstable
then switch Kernel to use _CoreFreq_ as the clock source
echo "corefreq" > /sys/devices/system/clocksource/clocksource0/current_clocksource
All the possible options can be listed with:
modinfo corefreqk.ko
I recommend to build my TSC implementation with clock source:
make DELAY_TSC=1 clean all
All building options:
make help
- About your cooling issues, I bet it's not so easy to cool a TR; in the UI at Processor window; experimental mode enabled and CPB disabled, you can change the
2Cratio down to3. With my 3950X, it gives a300MHz idle frequency.
You may have to select a target P-State ratioTGTconsequently, depending of which CPU-Freq is currently running.
cyring
on 22 Nov 2020
This is the test with default acpi_cpufreq with boost enabled and working afaict, and with the changes to corefreqk.h. When using the CoreFreq module as the governor, the API to manage the parameters are the same as the default one? will the apps know how to turn on and of the boost?
$ ./corefreq-cli -k
Linux:
|- Release [5.9.10]
|- Version [#1 SMP Sun Nov 22 17:46:46 CET 2020]
|- Machine [x86_64]
Memory:
|- Total RAM 65780696 KB
|- Shared RAM 151696 KB
|- Free RAM 53067860 KB
|- Buffer RAM 5852 KB
|- Total High 0 KB
|- Free High 0 KB
CPU-Freq driver [ acpi-cpufreq]
Governor [ ondemand]
CPU-Idle driver [ acpi_idle]
|- Idle Limit [ C2]
|- State POLL C1 C2
|- CPUIDLE ACPI FF ACPI IO
|- Power -1 0 0
|- Latency 0 1 400
|- Residency 0 2 800
$ ./corefreq-cli -s
Processor [AMD Ryzen Threadripper 3970X 32-Core Processor]
|- Architecture [Zen2/Castle Peak]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x08301025]
|- Signature [ 8F_31]
|- Stepping [ 0]
|- Online CPU [ 64/ 64]
|- Base Clock [100.001]
|- Frequency (MHz) Ratio
Min 400.00 < 4 >
Max 3700.02 < 37 >
|- Factory [100.000]
3700 [ 37 ]
|- Performance
|- P-State
TGT 2200.01 < 22 >
|- Turbo Boost [ UNLOCK]
XFR 4600.03 [ 46 ]
CPB 4500.03 [ 45 ]
1C 2800.02 < 28 >
2C 2200.01 < 22 >
|- Uncore [ LOCK]
Min 1800.01 [ 18 ]
Max 1800.01 [ 18 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH/O [Y/Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast-String Operation Fast-Strings [Missing]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Missing]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
Technologies
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [OFF]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 0]
|- Counters: General Fixed
| 6 x 64 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U <OFF>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [ ON]
|- Core C-States
|- C-States Base Address BAR [ 0x813 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Performance Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power & Thermal
|- Clock Modulation ODCM [Disable]
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP [ 0]
|- Junction Temperature TjMax [ 49: 12]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [Capable]
|- Thermal Monitor 2 HTC [Capable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
This is the test with default
acpi_cpufreqwith boost enabled and working afaict, and with the changes tocorefreqk.h. When using the CoreFreq module as the governor, the API to manage the parameters are the same as the default one? will the apps know how to turn on and of the boost?$ ./corefreq-cli -k ... CPU-Freq driver [ acpi-cpufreq] Governor [ ondemand] CPU-Idle driver [ acpi_idle] ...$ ./corefreq-cli -s Processor [AMD Ryzen Threadripper 3970X 32-Core Processor] |- Architecture [Zen2/Castle Peak] |- Vendor ID [AuthenticAMD] |- Microcode [0x08301025] |- Signature [ 8F_31] |- Stepping [ 0] ... |- Turbo Boost [ UNLOCK] XFR 4600.03 [ 46 ] CPB 4500.03 [ 45 ] 1C 2800.02 < 28 > 2C 2200.01 < 22 > Technologies |- Core Performance Boost CPB < ON> ...
It looks great, thank you. This confirms that _CoreFreq_ is able to detect the CPB & XFR ratios from a Zen2 / ThreadRipper.
The CPU-Freq framework is providing the attribute files in
/sys
When _CoreFreq_ is well registered as the governor and the back-end driver, it will receive any request made to those files.
$ ./corefreq-cli -k
Linux:
|- Release [5.9.10-arch1-1]
|- Version [#1 SMP PREEMPT Mon, 23 Nov 2020 12:11:12 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 32853064 KB
|- Shared RAM 108144 KB
|- Free RAM 30776768 KB
|- Buffer RAM 111896 KB
|- Total High 0 KB
|- Free High 0 KB
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ corefreqk-idle]
|- Idle Limit < C2>
|- State POLL C1 C2
|- CPUIDLE ZEN-C1 ZEN-C2
|- Power -1 0 0
|- Latency 0 1 400
|- Residency 0 2 800
In short you have many ways to disable Boost with _CoreFreq_:
- during its driver startup
- writing into the
/sys/devices/system/cpu/cpufreq/boostfile - at any time in the UI Technologies window
cyring
on 24 Nov 2020
Please try the development branch: develop
If anyone has residual or new issues, please create a new issue.
cyring
on 7 Dec 2020
Hello,
I have made some changes which also impact Threadripper.
After observing the registers addresses from SMU, it seems they are based on CCD but also on CCX.
Could you please give a try to the develop branch and check the Core's Temperature, Voltage and Power ?
Regards,
Cyril
cyring
on 12 Jan 2021
Since the last time I tested I have included a new cooling system on the 3970X, it is now water cooled. So that have quite an impact on the system and the CPU temps.
First thing I notice is that the package watts in idle sit around 40-50 instead of 70W for the Package.
The problem with the Core Boost persist, now with kernel 5.10.7, turbo does not go beyond 3.7GHz on Linux, still has the ACPI errors.
gdiazlo
on 16 Jan 2021
Since the last time I tested I have included a new cooling system on the 3970X, it is now water cooled. So that have quite an impact on the system and the CPU temps.
First thing I notice is that the package watts in idle sit around 40-50 instead of 70W for the Package.
Thanks for your return.
I can see now that the base address I have fixed for Castle Peak does not produce code regressions.
_Multi-dies_ processors may have different readings based on Pkg or CCD or CCX or a combination of them which could lead to adjacent base addresses to query from.
What _CoreFreq_ shows as the Package values (Temp, Power, Voltage) are queried with what I call the _ServiceProcessor_, which is just one selected CPU among all of them.
Choosing a _ServiceProcessor_ bound to a different cluster may reveal another reading ?
- Print the topology of Press key [
m] in the UI
corefreq-cli -m
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 65536 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 65536 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 65536 16w
003: 0 6 0 0 3 0 32 8 32 8 512 8 i 65536 16w
004: 0 8 0 1 4 0 32 8 32 8 512 8 i 65536 16w
005: 0 10 0 1 5 0 32 8 32 8 512 8 i 65536 16w
006: 0 12 0 1 6 0 32 8 32 8 512 8 i 65536 16w
007: 0 14 0 1 7 0 32 8 32 8 512 8 i 65536 16w
008: 0 16 1 2 8 0 32 8 32 8 512 8 i 65536 16w
009: 0 18 1 2 9 0 32 8 32 8 512 8 i 65536 16w
010: 0 20 1 2 10 0 32 8 32 8 512 8 i 65536 16w
...
- Restart the driver to bind a CPU as a service processor.
modinfo corefreqk.ko
...
parm: ServiceProcessor:Select a CPU to run services with (int)
...
- I'm choosing CPU
008because I'm targeting the CCD1
insmod ServiceProcessor=8
corefreqd
corefreq-cli
- Here, Core
008, and its SMT sibling024(*) are highlighted by the UI to remind you they are assigned to the Service queries.
Write down you package watts and restart (**) the driver, choosing another CPU as _ServiceProcessor_, and check if package watts are somehow constant or different based on the cluster the CPU belongs to.
(*) _with Hyper-threading enabled, the queries load is atomically distributed because of shared L1 cache_
(**) _when disabling a CPU, using the UI HotPlug menu and if the CPU was the _ServiceProcessor_ then _CoreFreq_ will search and reassign automatically the Services to another couple of {Core, SMT}_
The problem with the Core Boost persist, now with kernel 5.10.7, turbo does not go beyond 3.7GHz on Linux, still has the ACPI errors.
Only Linux, not Windows ?
cyring
on 16 Jan 2021
Could you also show me your Threadripper Power TDP Min Max PPT EDC TDC ?
cyring
on 16 Jan 2021
@gdiazlo : Hello, I have the issue #219 where Temperature per CCD does not reach a valid SMU register.
Using your 3970X and based on the develop branch, could you post the topology and one run of the sensors monitoring:
corefreq-cli -m
corefreq-cli -C
Thank you for your help.
cyring
on 21 Jan 2021
I'll do it as soon as I can. I hope before the weekend. These weeks I'm quite busy :(
gdiazlo
on 21 Jan 2021
Hello
The issue with turbo only happens on linux. A given core does not reach beyond 3.7GHz.
The output with ServiceProcessor=12 looks simmilar to the one without ServiceProcessor parameter.
These are the outpouts with the latest commit to develop, and kernel 5.10.9.
Power, current & thermal capture:
$ ./corefreq-cli -m
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 131072 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 131072 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 131072 16w
003: 0 6 0 0 3 0 32 8 32 8 512 8 i 131072 16w
004: 0 8 0 1 4 0 32 8 32 8 512 8 i 131072 16w
005: 0 10 0 1 5 0 32 8 32 8 512 8 i 131072 16w
006: 0 12 0 1 6 0 32 8 32 8 512 8 i 131072 16w
007: 0 14 0 1 7 0 32 8 32 8 512 8 i 131072 16w
008: 0 16 2 2 8 0 32 8 32 8 512 8 i 131072 16w
009: 0 18 2 2 9 0 32 8 32 8 512 8 i 131072 16w
010: 0 20 2 2 10 0 32 8 32 8 512 8 i 131072 16w
011: 0 22 2 2 11 0 32 8 32 8 512 8 i 131072 16w
012: 0 24 2 3 12 0 32 8 32 8 512 8 i 131072 16w
013: 0 26 2 3 13 0 32 8 32 8 512 8 i 131072 16w
014: 0 28 2 3 14 0 32 8 32 8 512 8 i 131072 16w
015: 0 30 2 3 15 0 32 8 32 8 512 8 i 131072 16w
016: 0 32 4 4 16 0 32 8 32 8 512 8 i 131072 16w
017: 0 34 4 4 17 0 32 8 32 8 512 8 i 131072 16w
018: 0 36 4 4 18 0 32 8 32 8 512 8 i 131072 16w
019: 0 38 4 4 19 0 32 8 32 8 512 8 i 131072 16w
020: 0 40 4 5 20 0 32 8 32 8 512 8 i 131072 16w
021: 0 42 4 5 21 0 32 8 32 8 512 8 i 131072 16w
022: 0 44 4 5 22 0 32 8 32 8 512 8 i 131072 16w
023: 0 46 4 5 23 0 32 8 32 8 512 8 i 131072 16w
024: 0 48 6 6 24 0 32 8 32 8 512 8 i 131072 16w
025: 0 50 6 6 25 0 32 8 32 8 512 8 i 131072 16w
026: 0 52 6 6 26 0 32 8 32 8 512 8 i 131072 16w
027: 0 54 6 6 27 0 32 8 32 8 512 8 i 131072 16w
028: 0 56 6 7 28 0 32 8 32 8 512 8 i 131072 16w
029: 0 58 6 7 29 0 32 8 32 8 512 8 i 131072 16w
030: 0 60 6 7 30 0 32 8 32 8 512 8 i 131072 16w
031: 0 62 6 7 31 0 32 8 32 8 512 8 i 131072 16w
032: 0 1 0 0 0 1 32 8 32 8 512 8 i 131072 16w
033: 0 3 0 0 1 1 32 8 32 8 512 8 i 131072 16w
034: 0 5 0 0 2 1 32 8 32 8 512 8 i 131072 16w
035: 0 7 0 0 3 1 32 8 32 8 512 8 i 131072 16w
036: 0 9 0 1 4 1 32 8 32 8 512 8 i 131072 16w
037: 0 11 0 1 5 1 32 8 32 8 512 8 i 131072 16w
038: 0 13 0 1 6 1 32 8 32 8 512 8 i 131072 16w
039: 0 15 0 1 7 1 32 8 32 8 512 8 i 131072 16w
040: 0 17 2 2 8 1 32 8 32 8 512 8 i 131072 16w
041: 0 19 2 2 9 1 32 8 32 8 512 8 i 131072 16w
042: 0 21 2 2 10 1 32 8 32 8 512 8 i 131072 16w
043: 0 23 2 2 11 1 32 8 32 8 512 8 i 131072 16w
044: 0 25 2 3 12 1 32 8 32 8 512 8 i 131072 16w
045: 0 27 2 3 13 1 32 8 32 8 512 8 i 131072 16w
046: 0 29 2 3 14 1 32 8 32 8 512 8 i 131072 16w
047: 0 31 2 3 15 1 32 8 32 8 512 8 i 131072 16w
048: 0 33 4 4 16 1 32 8 32 8 512 8 i 131072 16w
049: 0 35 4 4 17 1 32 8 32 8 512 8 i 131072 16w
050: 0 37 4 4 18 1 32 8 32 8 512 8 i 131072 16w
051: 0 39 4 4 19 1 32 8 32 8 512 8 i 131072 16w
052: 0 41 4 5 20 1 32 8 32 8 512 8 i 131072 16w
053: 0 43 4 5 21 1 32 8 32 8 512 8 i 131072 16w
054: 0 45 4 5 22 1 32 8 32 8 512 8 i 131072 16w
055: 0 47 4 5 23 1 32 8 32 8 512 8 i 131072 16w
056: 0 49 6 6 24 1 32 8 32 8 512 8 i 131072 16w
057: 0 51 6 6 25 1 32 8 32 8 512 8 i 131072 16w
058: 0 53 6 6 26 1 32 8 32 8 512 8 i 131072 16w
059: 0 55 6 6 27 1 32 8 32 8 512 8 i 131072 16w
060: 0 57 6 7 28 1 32 8 32 8 512 8 i 131072 16w
061: 0 59 6 7 29 1 32 8 32 8 512 8 i 131072 16w
062: 0 61 6 7 30 1 32 8 32 8 512 8 i 131072 16w
063: 0 63 6 7 31 1 32 8 32 8 512 8 i 131072 16w
$ ./corefreq-cli -C
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 15.34 72 1.1000 35 000000000000001430 0.021820068 0.021820068
001 13.29 72 1.1000 35 000000000000001115 0.017013550 0.017013550
002 5.48 72 1.1000 35 000000000000000622 0.009490967 0.009490967
003 11.48 72 1.1000 35 000000000000001178 0.017974854 0.017974854
004 11.38 72 1.1000 35 000000000000002781 0.042434692 0.042434692
005 24.58 72 1.1000 35 000000000000002407 0.036727905 0.036727905
006 4.74 72 1.1000 35 000000000000001170 0.017852783 0.017852783
007 5.97 72 1.1000 35 000000000000001348 0.020568848 0.020568848
008 0.57 72 1.1000 33 000000000000000044 0.000671387 0.000671387
009 0.82 72 1.1000 33 000000000000000016 0.000244141 0.000244141
010 0.74 72 1.1000 33 000000000000000175 0.002670288 0.002670288
011 0.84 72 1.1000 33 000000000000000258 0.003936768 0.003936768
012 2.81 72 1.1000 33 000000000000000425 0.006484985 0.006484985
013 0.65 72 1.1000 33 000000000000000018 0.000274658 0.000274658
014 0.58 72 1.1000 33 000000000000000013 0.000198364 0.000198364
015 0.89 72 1.1000 33 000000000000000063 0.000961304 0.000961304
016 5.37 72 1.1000 34 000000000000000928 0.014160156 0.014160156
017 6.63 72 1.1000 34 000000000000001538 0.023468018 0.023468018
018 58.73 72 1.1000 34 000000000000004983 0.076034546 0.076034546
019 4.96 72 1.1000 34 000000000000000572 0.008728027 0.008728027
020 269.49 72 1.1000 34 000000000000036720 0.560302734 0.560302734
021 79.48 72 1.1000 34 000000000000035300 0.538635254 0.538635254
022 53.41 72 1.1000 34 000000000000034417 0.525161743 0.525161743
023 64.39 72 1.1000 34 000000000000028488 0.434692383 0.434692383
024 1.33 72 1.1000 32 000000000000000025 0.000381470 0.000381470
025 0.48 72 1.1000 32 000000000000000015 0.000228882 0.000228882
026 0.60 72 1.1000 32 000000000000000128 0.001953125 0.001953125
027 1.10 72 1.1000 32 000000000000000078 0.001190186 0.001190186
028 0.49 72 1.1000 32 000000000000000149 0.002273560 0.002273560
029 0.57 72 1.1000 32 000000000000000014 0.000213623 0.000213623
030 0.50 72 1.1000 32 000000000000000013 0.000198364 0.000198364
031 0.51 72 1.1000 32 000000000000000015 0.000228882 0.000228882
032 3.49 72 1.1000 35 000000000000000000 0.000000000 0.000000000
033 4.02 72 1.1000 35 000000000000000000 0.000000000 0.000000000
034 10.50 72 1.1000 35 000000000000000000 0.000000000 0.000000000
035 7.18 72 1.1000 35 000000000000000000 0.000000000 0.000000000
036 30.54 72 1.1000 35 000000000000000000 0.000000000 0.000000000
037 16.02 72 1.1000 35 000000000000000000 0.000000000 0.000000000
038 11.16 72 1.1000 35 000000000000000000 0.000000000 0.000000000
039 13.51 72 1.1000 35 000000000000000000 0.000000000 0.000000000
040 4.43 72 1.1000 33 000000000000000000 0.000000000 0.000000000
041 0.50 72 1.1000 33 000000000000000000 0.000000000 0.000000000
042 0.62 72 1.1000 33 000000000000000000 0.000000000 0.000000000
043 0.51 72 1.1000 33 000000000000000000 0.000000000 0.000000000
044 0.54 72 1.1000 33 000000000000000000 0.000000000 0.000000000
045 0.51 72 1.1000 33 000000000000000000 0.000000000 0.000000000
046 0.50 72 1.1000 33 000000000000000000 0.000000000 0.000000000
047 6.91 72 1.1000 33 000000000000000000 0.000000000 0.000000000
048 7.80 72 1.1000 34 000000000000000000 0.000000000 0.000000000
049 13.90 72 1.1000 34 000000000000000000 0.000000000 0.000000000
050 14.94 72 1.1000 34 000000000000000000 0.000000000 0.000000000
051 3.15 72 1.1000 34 000000000000000000 0.000000000 0.000000000
052 16.34 72 1.1000 34 000000000000000000 0.000000000 0.000000000
053 153.17 72 1.1000 34 000000000000000000 0.000000000 0.000000000
054 176.51 72 1.1000 34 000000000000000000 0.000000000 0.000000000
055 51.97 72 1.1000 34 000000000000000000 0.000000000 0.000000000
056 1.02 72 1.1000 32 000000000000000000 0.000000000 0.000000000
057 0.77 72 1.1000 32 000000000000000000 0.000000000 0.000000000
058 0.53 72 1.1000 32 000000000000000000 0.000000000 0.000000000
059 0.65 72 1.1000 32 000000000000000000 0.000000000 0.000000000
060 1.94 72 1.1000 32 000000000000000000 0.000000000 0.000000000
061 0.59 72 1.1000 32 000000000000000000 0.000000000 0.000000000
062 0.59 72 1.1000 32 000000000000000000 0.000000000 0.000000000
063 0.63 72 1.1000 32 000000000000000000 0.000000000 0.000000000
Package Cores Uncore Memory
Energy(J): 68.164215088 2.387176514 12.301727295 0.000000000
Power(W) : 68.164215088 2.387176514 12.301727295 0.000000000
Now with ServiceProcesor=12 when loading the kernel module:
$ ./corefreq-cli -m
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 131072 16w
001: 0 2 0 0 1 0 32 8 32 8 512 8 i 131072 16w
002: 0 4 0 0 2 0 32 8 32 8 512 8 i 131072 16w
003: 0 6 0 0 3 0 32 8 32 8 512 8 i 131072 16w
004: 0 8 0 1 4 0 32 8 32 8 512 8 i 131072 16w
005: 0 10 0 1 5 0 32 8 32 8 512 8 i 131072 16w
006: 0 12 0 1 6 0 32 8 32 8 512 8 i 131072 16w
007: 0 14 0 1 7 0 32 8 32 8 512 8 i 131072 16w
008: 0 16 2 2 8 0 32 8 32 8 512 8 i 131072 16w
009: 0 18 2 2 9 0 32 8 32 8 512 8 i 131072 16w
010: 0 20 2 2 10 0 32 8 32 8 512 8 i 131072 16w
011: 0 22 2 2 11 0 32 8 32 8 512 8 i 131072 16w
012: 0 24 2 3 12 0 32 8 32 8 512 8 i 131072 16w
013: 0 26 2 3 13 0 32 8 32 8 512 8 i 131072 16w
014: 0 28 2 3 14 0 32 8 32 8 512 8 i 131072 16w
015: 0 30 2 3 15 0 32 8 32 8 512 8 i 131072 16w
016: 0 32 4 4 16 0 32 8 32 8 512 8 i 131072 16w
017: 0 34 4 4 17 0 32 8 32 8 512 8 i 131072 16w
018: 0 36 4 4 18 0 32 8 32 8 512 8 i 131072 16w
019: 0 38 4 4 19 0 32 8 32 8 512 8 i 131072 16w
020: 0 40 4 5 20 0 32 8 32 8 512 8 i 131072 16w
021: 0 42 4 5 21 0 32 8 32 8 512 8 i 131072 16w
022: 0 44 4 5 22 0 32 8 32 8 512 8 i 131072 16w
023: 0 46 4 5 23 0 32 8 32 8 512 8 i 131072 16w
024: 0 48 6 6 24 0 32 8 32 8 512 8 i 131072 16w
025: 0 50 6 6 25 0 32 8 32 8 512 8 i 131072 16w
026: 0 52 6 6 26 0 32 8 32 8 512 8 i 131072 16w
027: 0 54 6 6 27 0 32 8 32 8 512 8 i 131072 16w
028: 0 56 6 7 28 0 32 8 32 8 512 8 i 131072 16w
029: 0 58 6 7 29 0 32 8 32 8 512 8 i 131072 16w
030: 0 60 6 7 30 0 32 8 32 8 512 8 i 131072 16w
031: 0 62 6 7 31 0 32 8 32 8 512 8 i 131072 16w
032: 0 1 0 0 0 1 32 8 32 8 512 8 i 131072 16w
033: 0 3 0 0 1 1 32 8 32 8 512 8 i 131072 16w
034: 0 5 0 0 2 1 32 8 32 8 512 8 i 131072 16w
035: 0 7 0 0 3 1 32 8 32 8 512 8 i 131072 16w
036: 0 9 0 1 4 1 32 8 32 8 512 8 i 131072 16w
037: 0 11 0 1 5 1 32 8 32 8 512 8 i 131072 16w
038: 0 13 0 1 6 1 32 8 32 8 512 8 i 131072 16w
039: 0 15 0 1 7 1 32 8 32 8 512 8 i 131072 16w
040: 0 17 2 2 8 1 32 8 32 8 512 8 i 131072 16w
041: 0 19 2 2 9 1 32 8 32 8 512 8 i 131072 16w
042: 0 21 2 2 10 1 32 8 32 8 512 8 i 131072 16w
043: 0 23 2 2 11 1 32 8 32 8 512 8 i 131072 16w
044: 0 25 2 3 12 1 32 8 32 8 512 8 i 131072 16w
045: 0 27 2 3 13 1 32 8 32 8 512 8 i 131072 16w
046: 0 29 2 3 14 1 32 8 32 8 512 8 i 131072 16w
047: 0 31 2 3 15 1 32 8 32 8 512 8 i 131072 16w
048: 0 33 4 4 16 1 32 8 32 8 512 8 i 131072 16w
049: 0 35 4 4 17 1 32 8 32 8 512 8 i 131072 16w
050: 0 37 4 4 18 1 32 8 32 8 512 8 i 131072 16w
051: 0 39 4 4 19 1 32 8 32 8 512 8 i 131072 16w
052: 0 41 4 5 20 1 32 8 32 8 512 8 i 131072 16w
053: 0 43 4 5 21 1 32 8 32 8 512 8 i 131072 16w
054: 0 45 4 5 22 1 32 8 32 8 512 8 i 131072 16w
055: 0 47 4 5 23 1 32 8 32 8 512 8 i 131072 16w
056: 0 49 6 6 24 1 32 8 32 8 512 8 i 131072 16w
057: 0 51 6 6 25 1 32 8 32 8 512 8 i 131072 16w
058: 0 53 6 6 26 1 32 8 32 8 512 8 i 131072 16w
059: 0 55 6 6 27 1 32 8 32 8 512 8 i 131072 16w
060: 0 57 6 7 28 1 32 8 32 8 512 8 i 131072 16w
061: 0 59 6 7 29 1 32 8 32 8 512 8 i 131072 16w
062: 0 61 6 7 30 1 32 8 32 8 512 8 i 131072 16w
063: 0 63 6 7 31 1 32 8 32 8 512 8 i 131072 16w
$ ./corefreq-cli -C
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 13.74 72 1.1000 35 000000000000000707 0.010787964 0.010787964
001 8.01 72 1.1000 35 000000000000000741 0.011306763 0.011306763
002 5.39 72 1.1000 35 000000000000000947 0.014450073 0.014450073
003 2.18 72 1.1000 35 000000000000000700 0.010681152 0.010681152
004 67.78 72 1.1000 35 000000000000005395 0.082321167 0.082321167
005 23.04 72 1.1000 35 000000000000001724 0.026306152 0.026306152
006 17.42 72 1.1000 35 000000000000001537 0.023452759 0.023452759
007 10.81 72 1.1000 35 000000000000002773 0.042312622 0.042312622
008 253.03 72 1.1000 33 000000000000028262 0.431243896 0.431243896
009 24.17 72 1.1000 33 000000000000025567 0.390121460 0.390121460
010 114.73 72 1.1000 33 000000000000027645 0.421829224 0.421829224
011 69.04 72 1.1000 33 000000000000024913 0.380142212 0.380142212
012 0.69 72 1.1000 33 000000000000000122 0.001861572 0.001861572
013 0.95 72 1.1000 33 000000000000000169 0.002578735 0.002578735
014 6.59 72 1.1000 33 000000000000000479 0.007308960 0.007308960
015 0.70 72 1.1000 33 000000000000000094 0.001434326 0.001434326
016 1.26 72 1.1000 33 000000000000000041 0.000625610 0.000625610
017 1.11 72 1.1000 33 000000000000000037 0.000564575 0.000564575
018 1.79 72 1.1000 33 000000000000000036 0.000549316 0.000549316
019 3.53 72 1.1000 33 000000000000000278 0.004241943 0.004241943
020 0.55 72 1.1000 33 000000000000000019 0.000289917 0.000289917
021 0.77 72 1.1000 33 000000000000000123 0.001876831 0.001876831
022 0.57 72 1.1000 33 000000000000000018 0.000274658 0.000274658
023 15.76 72 1.1000 33 000000000000000653 0.009963989 0.009963989
024 0.53 72 1.1000 32 000000000000000883 0.013473511 0.013473511
025 1.24 72 1.1000 32 000000000000000024 0.000366211 0.000366211
026 15.18 72 1.1000 32 000000000000001634 0.024932861 0.024932861
027 11.51 72 1.1000 32 000000000000001496 0.022827148 0.022827148
028 0.74 72 1.1000 32 000000000000000115 0.001754761 0.001754761
029 3.45 72 1.1000 32 000000000000000157 0.002395630 0.002395630
030 0.63 72 1.1000 32 000000000000000167 0.002548218 0.002548218
031 0.52 72 1.1000 32 000000000000000165 0.002517700 0.002517700
032 0.82 72 1.1000 35 000000000000000000 0.000000000 0.000000000
033 2.76 72 1.1000 35 000000000000000000 0.000000000 0.000000000
034 13.16 72 1.1000 35 000000000000000000 0.000000000 0.000000000
035 4.07 72 1.1000 35 000000000000000000 0.000000000 0.000000000
036 12.56 72 1.1000 35 000000000000000000 0.000000000 0.000000000
037 6.56 72 1.1000 35 000000000000000000 0.000000000 0.000000000
038 3.53 72 1.1000 35 000000000000000000 0.000000000 0.000000000
039 32.15 72 1.1000 35 000000000000000000 0.000000000 0.000000000
040 3.93 72 1.1000 33 000000000000000000 0.000000000 0.000000000
041 149.07 72 1.1000 33 000000000000000000 0.000000000 0.000000000
042 109.33 72 1.1000 33 000000000000000000 0.000000000 0.000000000
043 100.67 72 1.1000 33 000000000000000000 0.000000000 0.000000000
044 0.72 72 1.1000 33 000000000000000000 0.000000000 0.000000000
045 1.98 72 1.1000 33 000000000000000000 0.000000000 0.000000000
046 1.15 72 1.1000 33 000000000000000000 0.000000000 0.000000000
047 0.57 72 1.1000 33 000000000000000000 0.000000000 0.000000000
048 0.57 72 1.1000 33 000000000000000000 0.000000000 0.000000000
049 0.62 72 1.1000 33 000000000000000000 0.000000000 0.000000000
050 0.65 72 1.1000 33 000000000000000000 0.000000000 0.000000000
051 0.47 72 1.1000 33 000000000000000000 0.000000000 0.000000000
052 0.48 72 1.1000 33 000000000000000000 0.000000000 0.000000000
053 0.52 72 1.1000 33 000000000000000000 0.000000000 0.000000000
054 0.47 72 1.1000 33 000000000000000000 0.000000000 0.000000000
055 0.49 72 1.1000 33 000000000000000000 0.000000000 0.000000000
056 16.40 72 1.1000 32 000000000000000000 0.000000000 0.000000000
057 0.79 72 1.1000 32 000000000000000000 0.000000000 0.000000000
058 6.90 72 1.1000 32 000000000000000000 0.000000000 0.000000000
059 5.91 72 1.1000 32 000000000000000000 0.000000000 0.000000000
060 0.67 72 1.1000 32 000000000000000000 0.000000000 0.000000000
061 0.89 72 1.1000 32 000000000000000000 0.000000000 0.000000000
062 0.62 72 1.1000 32 000000000000000000 0.000000000 0.000000000
063 0.52 72 1.1000 32 000000000000000000 0.000000000 0.000000000
Package Cores Uncore Memory
Energy(J): 67.808105469 1.947341919 11.654266357 0.000000000
Power(W) : 67.808105469 1.947341919 11.654266357 0.000000000
For the record, I had some help solving the Core Boost / XFR setting on Linux. Seems AMD only supports RAM speeds up to 3200MHz, if you load a profile with XMP with sets the RAM speed to 3600, depending on your silicon lottery it might work or not. On my case it didn't work. Setting a manual speed of 3533 MHz solved the issue, and now the CPU boost clocks as expected.
gdiazlo
on 8 Mar 2021
For the record, I had some help solving the Core Boost / XFR setting on Linux. Seems AMD only supports RAM speeds up to 3200MHz, if you load a profile with XMP with sets the RAM speed to 3600, depending on your silicon lottery it might work or not. On my case it didn't work. Setting a manual speed of 3533 MHz solved the issue, and now the CPU boost clocks as expected.
Here 3950X w/ dual g.skill 3600 going at 3733MHz cl 16. Bus 1866 and voltage 1.35
No Docp
cyring
on 8 Mar 2021
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