Vamiga: Test CPU/C/CHK1 fails

[dirkwhoffmann]

CHK instruction has a timing issue.

Amiga 500 8A: 🥰

vAmiga: 🙈

[emoon]

I think there are CPU cycle tests in the WinUAE cputester code now. Have you tried that out?

[dirkwhoffmann]

I think there are CPU cycle tests in the WinUAE cputester code now. Have you tried that out?

Yes, there are, but there were a few instructions for which I was unable to create working test cases (CHK was one of them). A couple of weeks ago, I've started to write these "timing stripe" tests in addition to the cputester timing tests. E.g., here is one for the ADD instructions:

In this test, I use COLOR00 as the operand source address. Since reading an OCS register has the side effect of writing some value into that register, I can "see" the exact cycle when the memory access happens. At the moment, cputester can "only" verify the total cycle count for an instruction. If I remember correctly, Toni had some clever ideas to measure this information, too. So we might see an even better cputester tool in future. The really cool thing about Tonis tool is that it runs a very large amount of test combinations with all kinds of different value / flag combinations whereas my color stripe tests only cover a very limited set of combinations. Fortunately, we don't have to choose between the two approaches. We can use both.

[emoon]

Yeah that makes sense

[dirkwhoffmann]

Much better now: 😎

BTW, test CPU/C/CHK3 revealed a huge bug in vAmiga. Up to now, it was a bad idea to use the CHK instruction in combination with a negative bound: 🙈

This has been fixed, too: 😎

CPU/C/CHK3 (Amiga 500 8A):

vAmiga (next release):

[mithrendal]

Up to now, it was a bad idea to use the CHK instruction in combination with a negative bound

strange I thought you tested randomly all opcodes combinations against Musashi ... back then when you decided to take Moira in favour of the Musashi core, no ? Maybe Musashi had the problem too with the negative bound ?🤔

[dirkwhoffmann]

strange I thought you tested randomly all opcodes combinations against Musashi

Yes, but the error was due to a missing return statement.which caused the CPU to perform a prefetch. This is not checked by the CPU test runner, because it only affects the execution of the next instruction (the values in the prefetch queue are wrong). Since Musashi's prefetch logic isn't very accurate, it is impossible to compare Moira's prefetch queue with the one in Musashi. And finally, the test runner could not detect the timing inaccuracy, because CHK has wrong timing in Musashi.