Runtime: [RyuJIT] Ensure all the VEX.vvvv instructions in IsDstDstSrc/DstSrcSrcAVXInstruction
Logging the conversation https://github.com/dotnet/coreclr/pull/18876#pullrequestreview-136452081
We should double check that all the instructions that use VEX.vvvv field (VEX encoded 256-bit and 128-bit instructions both) properly exist in IsDstDstSrc/DstSrcSrcAVXInstruction.
fiigii
All 7 comments
@fiigii @tannergooding do you envision that this is something we could do programmatically, e.g. by adding asserts?
CarolEidt
on 12 Jul 2018
do programmatically, e.g. by adding asserts?
Maybe hard because the current ins table does not have VEX encoding information. I think https://github.com/dotnet/coreclr/issues/14523 is a better approach.
fiigii
on 12 Jul 2018
@CarolEidt, I think we could after a refactoring to add the necessary flags/etc.
tannergooding
on 12 Jul 2018
This should be significantly easier to do now that this information is encoded as flags in the instruction table.
tannergooding
on 29 Aug 2018
@CarolEidt @tannergooding Is this something that will just be a one-time manual audit, or does code need to be written? Does this need to be in 3.0? If so, can someone take ownership?
BruceForstall
on 13 Mar 2019
This just needs to be a one time manual audit. I believe I already did this when I added the instruction flags support, but it wouldn't hurt for someone to do it again.
tannergooding
on 13 Mar 2019
I've gone through the instruction manual, and have found nothing immediately actionable. The only questionable thing I found is blendvps, blendvpd and pblendvb which "sort of" have IsDstDstSrc semantics, but since the mask is implicit xmm0 for SSE vs. encoded immediate for AVX, they really can't use the same emitter method anyway.
I think that these methods should be limited to those instructions that have both VEX and non-VEX encodings, but I believe there may still be some places in SIMD codegen that use the 2-operand emit method to generate 3-operand VEX-only instructions. And unfortunately, the emitter and instrDescs have only the most minimal of mechanisms to ensure that a supported format is being used.
I am going to close this, and add some notes to dotnet/runtime#9135.
CarolEidt
on 24 Apr 2019
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Most helpful comment
I've gone through the instruction manual, and have found nothing immediately actionable. The only questionable thing I found is
blendvps,blendvpdandpblendvbwhich "sort of" haveIsDstDstSrcsemantics, but since the mask is implicit xmm0 for SSE vs. encoded immediate for AVX, they really can't use the same emitter method anyway.I think that these methods should be limited to those instructions that have both VEX and non-VEX encodings, but I believe there may still be some places in SIMD codegen that use the 2-operand emit method to generate 3-operand VEX-only instructions. And unfortunately, the
emitterandinstrDescs have only the most minimal of mechanisms to ensure that a supported format is being used.I am going to close this, and add some notes to dotnet/runtime#9135.