Rack: gates out from step sequencer

[enricocosimi]

hello, first of all, many thanks for wonderful Rack!!!
It would be great to have Gates Output from Step Sequencer at 90% (better yet 50%) of PW.
Currently, if two adiacent steps are "on", their gates will fuse in a single, long event.

Still: why don't put under development some switching and boolean logic modules?

[AndrewBelt]

Our options are

1) Adjacent gates "will fuse in a single, long event", which is the v0.3.0 behavior.
2) Gate will turn off on each clock pulse, and then turn back on, which is the v0.3.1 (current) behavior.
3) Gate lasts P percent, for some hard-coded P. I don't like this at all, too arbitrary.

Grayscale Binary will be ported soon, which will make it possible to do (1), so I think I should revert back to (1) once this happens.

Also, in the future, report Fundamental issues to the https://github.com/VCVRack/Fundamental/issues Issue Tracker.

[synthi]

Why not having nº1 but also add a short trigger output??? or maybe a switch for tie gates (ala 0.3.0) but also a knob for controlling the gate lenght? Actually the gates are really long....

[AndrewBelt]

Noted, but I'd have to wait on Grayscale for any redesigns to the SEQ3 panel.

[AndrewBelt]

Fixed in the Fundamental repo, by reverting back to option (1).

How to turn a SEQ3 gate into triggers:

Make sure SEQ3 is clocked by an external source, and send a copy of the clock (through a multiple or the upcoming stackable cables) to a VCA's CV input. Connect the gate output of SEQ3 to the VCA's input, and the output should be the gate multiplied by the clock, i.e. a trigger whenever the gate is open.

Note that timing is important here. The VCA clock signal shouldn't be delayed even one sample before the Ext Clock signal. Remember that each cable introduces one sample of delay between modules.

[enricocosimi]

b.t.w., in a more CPU-expensive way, you can "re-shape" a standard Gate Out driving a standard ADSR Fundamental module (on Gate Input), then set all four controls at minimum and using the ADSR Env Out as "trigger reborn/reshaped" for TRIG IN on other modules... :-)

[martin-lueders]

Just an idea: Why not add an additional trigger out to the SEQ-3, which also will work with the internal clock? The sequencers in Softube have both a gate and a trigger out.

[AndrewBelt]

I'll ask Grayscale. I imagine there's not enough room.

[martin-lueders]

Hi Andrew, just a quick question which is not really an issue for the
github.

I noticed that I used the name "ML modules" with the space as the plugin
slug. I was wondering whether that might cause any problems, or whether it
is just any string. If the latter, why did you introduce two different
names?

If it might cause problems at some stage, I will rename it.

thanks,
Martin

On 25 September 2017 at 14:25, Andrew Belt [e-mail] wrote:

I'll ask Grayscale. I imagine there's not enough room.

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[AndrewBelt]

The slug is meant to be constant and it is the label used in saved patches. The title is independent from the slug and can be changed and include special characters.