Ghidra: Sleigh instruction with register in non contiguous bits

[pd0wm]

I'm trying to implement the MADDF.S reg1, reg2, reg3, reg4 instruction for the V850E2 architecure, see manual page 374.

The instruction is formatted as:
r r r r r 1 1 1 1 1 1 R R R R R | w w w w w 1 0 1 W 0 0 W W W W 0, where r = reg2, R = reg1, w = reg3, W = reg4.

However reg4, is not contiguous. The first W, is the least significant bit, W W W W is the rest. How do I represent this in the slaspec?

I already tried something along the lines of:

reg4: value is op1720 & op2323
    [ value = ((op1720 << 1) | op2323); ]   
    { export *[register]value; }        

but that doesn't seem to work properly, since I can't attach it to the register variables without getting an error. Does anyone have some pointers/documentation I can look at?

[esaulenka]

@pd0wm, as a workaround, in this case you can implement TWO register lists: r0..r15 and r16..lp(same as r31). Then you can test MSB (you made a typo, first W is a most significant bit in register number) and apply suitable register list.

Unfortunately, I don't know, how to write this in a single opcode constructor...

[GhidorahRex]

I think @esaulenka has the best suggestion here. Something along the lines of

attach variables [op0_1720] [r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15];
attach variables [op1_1720] [r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31];
reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; }
reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; }

If op2323 is actually the LSB, you could use the same trick but treat the first attach as the even registers, and second attach as the odd registers. You need two separate fields in order to attach them to distinct register lists.

[pd0wm]

Thanks! That did the trick: https://github.com/pd0wm/ghidra_v850/commit/6301512973be64a100652b59d2d66f0d9d75b56c

It's actually LSB, not sure why NEC/Renesas chose it that way.