Device-os: [Gen3] UART 8N2, 8E2, 7O1, 7E1, 7O2 and 7E2 modes support

[memaskal]

Feature/Enhancement Request

GEN 3 hardware support for more Serial configurations options, such as odd parity, and 7 and 9 bit modes, which are currently not available as stated in the official Particle documentation

[avtolstoy]

Unfortunately this is a hardware limitation of the microcontroller used on Gen 3 devices: nRF52840.

The only UART modes supported by the hardware are: 8N1, 8E1, 8N2 and 8E2.

We could _technically_ support 7O1, 7E1, 7O2, 7E2 by manually computing/checking the parity bit in software, so I suggest renaming the issue to something along the lines of '[Gen3] UART 7O1, 7E1, 7O2 and 7E2 modes support'.

PRs are always welcome as well :smile:

[ScruffR]

For completeness of the feature-request:
Currently the device OS only supports 8N1 & 8E1, so the HW capabilities for 8N2 & 8E2 would need implementing and software support for 8O1 & 8O2 should not be forgotten either.

Related forum post
https://community.particle.io/t/serial1-stop-bit-configuration-for-xenon/49801

[avtolstoy]

8N2 & 8E2

I thought we had those implemented, apparently not, I've changed the title to reflect that.

8O1 & 8O2

We won't be able to implement these even in software, because there is no 9-bit support at all.

[ScruffR]

@avtolstoy, any news on 8N2 and 8E2?
This would help with implementing DMX512 which uses 8N2.

Is it also at all possible to have a (mockup) USARTSerial::breakTx() function to allow for LIN-like communication? (::breakTx() and ::breakRx() exist for Gen2 but are not documented).

---

I went on for my own project and came up with this

                                                        // doc: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf
uint8_t * const pBase    = (uint8_t *)0x40002000;       // UARTE0 (UARTE1 .. 0x40028000) (doc. 6.34.9)
uint32_t* const pStartTX = (uint32_t*)&pBase[0x008];    // TASKS_STARTTX write 1 to initiate
uint32_t* const pStopTX  = (uint32_t*)&pBase[0x00C];    // TASKS_STARTTX write 1 to initiate
uint32_t* const pEnable  = (uint32_t*)&pBase[0x500];    // ENABLE register (doc. 6.34.9.6 Enable .. 8, Disable .. 0) 
uint32_t* const pConfig  = (uint32_t*)&pBase[0x56C];    // CONFIG register (doc. 6.34.9.18)

void breakTx(uint32_t duration = 100) {
  *pEnable  = 0;
  pinResetFast(TX);
  delayMicroseconds(duration);
  *pEnable  = 8;                                        // enabling takes ~14µs which should work as DMX512 ABM (~12µs)
}

void setup() {
  Serial1.begin(250000, SERIAL_8N2);                    // 8N2 will be treated as 8N1
  //*pStopTX  = 1;                                        // stop TX
  *pEnable  = 0;                                        // disable UARTE
  *pConfig |= (1 << 4);                                 // set 2 stop bits, no parity, no HW flow control
  *pEnable  = 8;                                        // enable UARTE
  //*pStartTX = 1;                                        // start TX
}

void loop() {
  breakTx(100);
  Serial1.write(someData, someLen);
  delay(1000);
}

[ScruffR]

@avtolstoy, I have also posted about the lack of 2 stop bit support on the nRF forum here
https://devzone.nordicsemi.com/f/nordic-q-a/54215/howto-use-uarte-250000-8n2-plus-txbreak-for-dmx512-protocol

and as it seems the nrf_uarte_config() function has not (yet) been updated to also cater for the "new" feature.
The proposed way to go is along the line I have posted above and shouldn't be too much of a problem adding after the current call of nrf_uarte_config().

In the latest nRFx dirver repo support for setting 2 stop bits is already available
https://github.com/NordicSemiconductor/nrfx/blob/master/hal/nrf_uarte.h#L146
but the function prototype has also changed
https://github.com/NordicSemiconductor/nrfx/blob/master/hal/nrf_uarte.h#L416