Corefreq: Support of Thermal Velocity Boost [TVB] : Intel i7-9750H
Arthav24
All 35 comments
Hello !
First, can you start _CoreFreq_ ?
- If yes, can you post the output of the followings:
corefreq-cli -s
corefreq-cli -m
corefreq-cli -u
corefreq-cli -M
corefreq-cli -k - If no, can you describe what is happening after loading its kernel module (dmesg, crash, ...)
cyring
on 26 Mar 2020
No , after succesfullly building it using
make MSR_CORE_PERF_UC=MSR_CORE_PERF_FIXED_CTR1 MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2
and then insmod corefreqk.ko
thows this
root@arthav-G7:/home/arthav/CoreFreq# insmod corefreqk.ko
insmod: ERROR: could not insert module corefreqk.ko: Operation not permitted
root@arthav-G7:/home/arthav/CoreFreq#
dmesg shows
[ 1138.472081] Lockdown: insmod: Loading of unsigned module is restricted; see man kernel_lockdown.7
Arthav24
on 27 Mar 2020
...
root@arthav-G7:/home/arthav/CoreFreq# insmod corefreqk.ko
insmod: ERROR: could not insert module corefreqk.ko: Operation not permitted
root@arthav-G7:/home/arthav/CoreFreq#dmesg shows
[ 1138.472081] Lockdown: insmod: Loading of unsigned module is restricted; see man kernel_lockdown.7
Solved @ https://github.com/cyring/CoreFreq/issues/167#issuecomment-588567507
You should have 2 options: sign the kernel module or disable the system signature enforcement.
regards
cyring
on 27 Mar 2020
after signing the module,
root@arthav-G7:/home/arthav/CoreFreq# corefreqd
Driver connection error code 13
Version 0.0.0: 'Permission denied' @ line 5526
Arthav24
on 27 Mar 2020
Something behaves wrongly : Version is 0.0.0
- Plz, check if errors appear in
dmesg? - Do you see the driver loaded ?
lsmod | grep corefreqk - Be sure to download / build and run only one source code
## as user
git clone https://github.com/cyring/CoreFreq.git
cd CoreFreq
make clean all
## as root, sign the module before loading it
insmod corefreqk.ko
./corefreqd
## as user, in another term
cd CoreFreq
./corefreq-cli
- If no results, then plz show me the followings:
cat /proc/cpuinfo
lspci -nn
- Are these the specs of your Processor ?
Especially the CPUID signature of Family = 06 and Model = 9e (in hexadecimal values)
If those match, then Processor belongs to Kabylake and it is supported here in the source code:
https://github.com/cyring/CoreFreq/blob/2f4cac48406c1e3e0bc3c7970c405c9bb94026f0/corefreqk.h#L5083
cyring
on 27 Mar 2020
yup finally it worked thanks ! seems like I messed up something with multiple sources as I cloned twice before
Arthav24
on 27 Mar 2020
Great !
Please let me know about your _CoreFreq_ experience.
Feel free to post screenshots that I'll gather into the Wiki such as:
https://github.com/cyring/CoreFreq/wiki/CPU-support
cyring
on 27 Mar 2020
Arthav24
on 27 Mar 2020
arthav@arthav-G7:~/CoreFreq$ ./corefreq-cli -s
Processor [Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz]
|- Architecture [Kaby Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [ 202]
|- Signature [ 06_9E]
|- Stepping [ 10]
|- Online CPU [ 12/ 12]
|- Base Clock [ 99.691]
|- Frequency (MHz) Ratio
Min 797.53 [ 8 ]
Max 2591.96 [ 26 ]
|- Factory [100.000]
2600 [ 26 ]
|- Performance
|- OSPM
TGT 4486.09 < 45 >
|- HWP
Min 797.53 < 8 >
Max 4486.09 < 45 >
TGT N/A < 0 >
|- Turbo Boost [ UNLOCK]
1C 4486.09 < 45 >
2C 4386.40 < 44 >
3C 4286.71 < 43 >
4C 4187.02 < 42 >
5C 4087.33 < 41 >
6C 3987.64 < 40 >
|- Uncore [ UNLOCK]
Min 797.53 < 8 >
Max 4187.02 < 42 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ UNLOCK]
|- Turbo Activation [ UNLOCK]
Nominal 2591.96 [ 26 ]
Level1 2193.20 [ 22 ]
Turbo 2492.27 [ 25 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX-512 [N] BMI1/BMI2 [Y/Y] CLFLUSH [Y] CMOV [Y]
|- CMPXCHG8B [Y] CMPXCHG16B [Y] F16C [Y] FPU [Y]
|- FXSR [Y] LAHF/SAHF [Y] MMX/Ext [Y/N] MONITOR/X[Y/N]
|- MOVBE [Y] MPX [Y] PCLMULQDQ [Y] POPCNT [Y]
|- RDRAND [Y] RDSEED [Y] RDTSCP [Y] SEP [Y]
|- SGX [Y] SSE [Y] SSE2 [Y] SSE3 [Y]
|- SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y] SYSCALL [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast-String Operation Fast-Strings [Capable]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing]
|- Architectural - Buffer Overwriting MD-CLEAR [Capable]
|- Architectural - Rogue Data Cache Load RDCL_NO [Missing]
|- Architectural - Enhanced IBRS IBRS_ALL [Missing]
|- Architectural - Return Stack Buffer Alternate RSBA [Missing]
|- Architectural - Speculative Store Bypass SSB_NO [Missing]
|- Architectural - Microarchitectural Data Sampling MDS_NO [Missing]
|- Architectural - TSX Asynchronous Abort TAA_NO [Missing]
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing]
Technologies
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 4]
|- Counters: General Fixed
| 4 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A < ON>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U < ON>
|- Frequency ID control FID [OFF]
|- Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP < ON>
|- Capabilities (MHz) Ratio
Lowest 99.69 [ 1 ]
Efficient 797.53 [ 8 ]
Guaranteed 2591.96 [ 26 ]
Highest 4486.09 [ 45 ]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 0]
|- I/O MWAIT Redirection IOMWAIT [Disable]
|- Max C-State Inclusion RANGE [ 0]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 2 4 1 1 1
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
Power & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP < 128>
|- Junction Temperature TjMax [ 0:100]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 45]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
please suggest me some undervolting utility for 9750h. I wish to undervolt it by 0.125mV
Arthav24
on 27 Mar 2020
please suggest me some undervolting utility for 9750h. I wish to undervolt it by 0.125mV
- i7-9750H added. Thank you
Beside BIOS, I don't see other _privileged_ mean to decrease the Vcore
Your Processor is
HWPcapable.
Go toMenu > Window > Power & Thermal > Energy Policy - HWP EPPto set it to a saving energy profile. This will lower Vcore, but unfortunately the Frequency also
cyring
on 27 Mar 2020
Happy to see i7-9750H in CPU support and Thanks for the mention :)
let me know if you want more info and screenshots. Just saying this also worked on i9-9900K. I tested that on office machine, after lockdown can get you some screenshots for that too.
Yeah that I know can set it more like 175 or 200 but I was thinking to decrease Vcore just like Throttlestop does in windows. I am not so sure but it is done by changing MSR values. After plundervolt fix pushed by intel and dell its impossible to undervolt by softwares like XTU and Throttlestop in windows , now its on Dell they implement basic Vcore offfset settings in BIOS for supported CPSs.
Arthav24
on 27 Mar 2020
... Yeah that I know can set it more like 175 or 200 but I was thinking to decrease Vcore just like Throttlestop does in windows. I am not so sure but it is done by changing MSR values. ...
Can you export data from Throttlestop (or source code) to know which MSRs is/are involved ?
cyring
on 27 Mar 2020
let me see if I can or if something available online about it.
Arthav24
on 27 Mar 2020
0x150 is the msr , the values being written to.
I found this
https://github.com/georgewhewell/undervolt
https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3b-part-2-manual.html
https://github.com/mihic/linux-intel-undervolt
Arthav24
on 27 Mar 2020
Yes I had searched for TVB, and I left some bits layout in the issue #121
MSR 0x150 ... set bit 63 to 1 and [39:32] to 18h
Bit 3 shows you if TVB is enabled or disabled (0=disabled).
- Suggestions to decode this register:
1- Linux: Using command linerdmsr -ax 0x150, plz post the output values of all Cores
2- Windows tools: change the settings to alter the Vcore as will; reading this MSR, before and after the change.
cyring
on 27 Mar 2020
surprisingly,
arthav@arthav-G7:~$ rdmsr -ax 0x150
arthav@arthav-G7:~$ sudo rdmsr -ax 0x150
No output in linux.
will post from windows soon
Arthav24
on 28 Mar 2020
surprisingly,
arthav@arthav-G7:~$ rdmsr -ax 0x150 arthav@arthav-G7:~$ sudo rdmsr -ax 0x150No output in linux.
will post from windows soon
- was kernel module
msr.kocorrectly loaded ? - might be this register is not supported b/c TVB is not available in 9750H ?
cyring
on 28 Mar 2020
1) root@arthav-G7:/home/arthav/CoreFreq# modinfo msr.ko
modinfo: ERROR: Module msr.ko not found.
after I loaded the msr
root@arthav-G7:/home/arthav/CoreFreq# modinfo msr
filename: /lib/modules/5.3.0-42-generic/kernel/arch/x86/kernel/msr.ko
license: GPL
description: x86 generic MSR driver
author: H. Peter Anvin hpa@zytor.com
srcversion: E88DB62FB5C5B69B9D18A1F
depends:
retpoline: Y
intree: Y
name: msr
vermagic: 5.3.0-42-generic SMP mod_unload
signat: PKCS#7
signer:
sig_key:
sig_hashalgo: md4
root@arthav-G7:/home/arthav/CoreFreq# rdmsr -ax 0x150
18593
18593
18593
18593
18593
18593
18593
18593
18593
18593
18593
18593
root@arthav-G7:/home/arthav/CoreFreq#
Arthav24
on 31 Mar 2020
EDIT
18593 converts to binary 11000010110010011
bit 63 equals zero, thus TVB is disabled
let's set this bit to one, and modify register on all cores
18593 OR 8000000000000000 = 8000000000018593
wrmsr -ax 0x150 0x8000000000018593
rdmsr -ax 0x150
the readings should output bit 3 set to one to confirm TVB has been enabled
800000000001859BDo some CoreFreq measurements before and after enabling TVB such as: the max frequency on single Core; Temperature ; Vcore; ...
You can stress from the[F2] Menu > Tools > Turbo Round RobinPlz post screenshots of the Frequency and Chipset views, before and after TVB
_Remarks_:
I like this calculator
I suggest you reopen this issue and name it "Support of Thermal Velocity Boost [TVB] : Intel i7-9750H"
I miss a CPUID leave to check the TVB capability in Processor : I need a TVB capability bit before altering the
0x150MSR. _Touching_ this register may crash a non capable Processor.
At least If we don't have such feature bit, I will have to maintain a _white-list_ table of capable Processors
cyring
on 31 Mar 2020
I was onto same what you asked, but when I tried to insmod corefreqk.ko this came
root@arthav-G7:/home/arthav/CoreFreq# insmod corefreqk.ko
insmod: ERROR: could not insert module corefreqk.ko: Invalid module format
so I ran make clean and make all and then signed again now its working fine.
then
root@arthav-G7:/home/arthav/CoreFreq# rdmsr -ax 0x150
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4
185c4 is 11000010111000100 means the 3rd bit is 0 so TVB must be disabled.
I dont know what happened between restarts that it changed the value of 0x150 from 18593 to 185c4.
so to enable it I tried to flip 3 bit to 1 so it will be 185cc or 11000010111001100
but arthav@arthav-G7:~$ sudo wrmsr -a 0x150 0x80000000000185CC
wrmsr: pwrite: Operation not permitted
here are some screen shots before enabling TVB
Arthav24
on 31 Mar 2020
I have searched _again_ in the last Intel SDM for MSR 0x150 specifications; and it is still undocumented.
So we have to rely on reversed engineering source codes...
So things found on the Internet say that:
- bit 3 is for the status : don't change it
- bit 63 allows to toggle the feature (which should be reflected in bit 3)
- one good thing is that reading / writing this MSR do not crash your Processor. Probably some bits can be changed and others not. You may get a working wrmsr for some of these.
- I suggest you observe the bits values before /after tweaking TVB from any tools, or BIOS (if available)
cyring
on 31 Mar 2020
I need to fix :
- Core i7-9750H of family
06_9Ebelongs to Coffee Lake - TVB is marked as None in Intel's datasheet. This might explain you can't write the MSR, but why can you still read something ?
cyring
on 31 Mar 2020
Yes the intel official page for i7-9750H marks support for TVB as No also I couldn't find anything in BIOS also related to TVB.
That explains the inability to write the particular bit although it was wrong still.
the 0x150 msr might contain some other supported feature bits thats why its reading something may be
Arthav24
on 1 Apr 2020
Unfortunately we need another CPU to develop this feature.
Meanwhile I have pushed in the develop branch, some Kaby Lake and Coffee Lake architecture name detection fixes. Could you give it a try and show me a screenshot please ?
cyring
on 1 Apr 2020
Arthav24
on 3 Apr 2020
Updated, thank you.
cyring
on 6 Apr 2020
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/4/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/5/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/6/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/7/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/8/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/9/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/10/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/11/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Read 0xf0000000 from /dev/cpu/0/msr
this I pulled from undervolt service output. May be you can integrate undervolting corefreq. That would be awesome Thanks
Arthav24
on 25 Apr 2020
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/4/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/5/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/6/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/7/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/8/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/9/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/10/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/11/msr
Apr 25 16:53:08 arthav-G7 undervolt.py[6256]: INFO:root:Read 0xf0000000 from /dev/cpu/0/msr
this I pulled from undervolt service output. May be you can integrate undervolting corefreq. That would be awesome Thanks
cyring
on 25 Apr 2020
- Did you got those msr from Core i7-9750H ?
(b/c last time we talked about, it was not TVB capable) - Why writing values onto CPUs starting at number 4 ; and then reading CPU number 0 ?
- Did you follow the Vcore through CoreFreq, while writing this MSR
0x150: did you observe the voltage change immediately ?
cyring
on 25 Apr 2020
1) Yes I pulled this from i7-9750H equipped Dell G7 7590
2) Tbt it also triggered curiosity in me too that why only writing to processors 4 to 11 !
3) Yes I noticed immediate change in Vcore in corefreq upon writing msr through undervolt.
Arthav24
on 25 Apr 2020
- According to the few source codes about subject, AC or DC could make a difference when tweaking msr
0x150. It may explain why our previous tests failed b/c of current mode. - TVB looks declined in planes: that could be the reason of the CPU numbers confusion
- Programming the TJ offset can also be combined with TVB. That's definitely a feature I want to add into _CoreFreq_
- I still don't know what's the scope of the msr
0x150, but if it follows a mailbox protocol, any and only one Core has to program it. - Most TVB apps, I have quickly studied, don't feel comfortable with programming the voltage offset:
- compute rounded negative value
- reciprocal computal check
- writing msr
- reading, comparing written value
...
cyring
on 25 Apr 2020
Sorry, It from my end I couldn't get the whole output as it was truncating itself.
Apr 26 11:57:11 arthav-G7 systemd[1]: Starting undervolt...
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Setting core offset to -125mV
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/1/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/2/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/3/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/4/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/5/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/6/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/7/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/8/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/9/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/10/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000011f0000000 to /dev/cpu/11/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/1/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/2/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/3/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/4/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/5/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/6/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/7/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/8/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/9/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/10/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000001000000000 to /dev/cpu/11/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Read 0xf0000000 from /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Setting cache offset to -125mV
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/1/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/2/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/3/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/4/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/5/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/6/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/7/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/8/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/9/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/10/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x80000211f0000000 to /dev/cpu/11/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/1/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/2/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/3/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/4/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/5/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/6/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/7/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/8/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/9/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/10/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Writing 0x8000021000000000 to /dev/cpu/11/msr
Apr 26 11:57:11 arthav-G7 undervolt.py[11515]: INFO:root:Read 0xf0000000 from /dev/cpu/0/msr
Apr 26 11:57:11 arthav-G7 systemd[1]: Started undervolt.
MSR 0x150
_based on 0x80000211f0000000_
SET| CLR | SEL | RSV | RSV | WRT| OFS | CLR
------|---------|---------|---------|----------|------|----------|--------
63|62:44|43:40|39:36|35:33|32 |31:21|20:0
0x1|0x0 |0x2 | 0x1 |0x0 |0x1|0x780|0x0
SELPlane Selector among those values
PLANE|SEL
---------|-------
CORE|0
GPU |1
CACHE Level ? |2
UNCORE IMC ?|3
OTHER|4
OFSVoltage Offset in decimal range [-1023,+1023]
SIGN|VALUE
-------|----------
31 | 30:21
0x1|896
Sources
cyring
on 26 Apr 2020
Moved to the Roadmap.
cyring
on 7 Dec 2020
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